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DAC8734_091 Datasheet(PDF) 7 Page - Texas Instruments |
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DAC8734_091 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 41 page  PIN CONFIGURATIONS CS SCLK SDI SDO LDAC RST GPIO-0 GPIO-1 UNI/BIP-A DGND AV DD V MON AV SS REFGND-B REF-B REF-A REFGND-A AV SS AGND AV DD 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 DAC8734 NC AV DD V MON AV SS REFGND-B REF-B REF-A REFGND-A AV SS AGND AV DD NC 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 NC CS SCLK SDI SDO LDAC RST GPIO-0 GPIO-1 UNI/BIP-A DGND NC DAC8734 DAC8734 www.ti.com .................................................................................................................................................. SBAS465A – MAY 2009 – REVISED SEPTEMBER 2009 RHA PACKAGE(1) PFB PACKAGE QFN-40 TQFP-48 (TOP VIEW) (TOP VIEW) (1) The thermal pad is internally connected to the substrate. This pad can be connected to AVSS or left floating. PIN DESCRIPTIONS PIN NO. PIN NAME QFN-40 TQFP-48 I/O DESCRIPTION SPI bus chip select input (active low). Data are not clocked into the SPI shift register unless CS is CS 1 2 I low. When CS is high, SDO is in a high-impedance state. SCLK 2 3 I SPI bus clock SDI 3 4 I SPI bus input data SDO 4 5 O SPI output data Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the LDAC 5 6 I contents of the Input Data Register are transferred to it. The DAC output changes to the corresponding level simultaneously when the DAC latch is updated. Reset input (active low). Logic low on this pin resets the input registers and DACs to the values RST 6 7 I defined by the UNI/BIP pins, and sets the Gain Register and Zero Register to default values. General-purpose digital input/output 0. This pin is a bidirectional, digital input/output, and has an GPIO-0 7 8 I/O open-drain output. A 10k Ω pull-up resistor to IOVDD is needed when this pin is used as an output. See the GPIO Pins section for details. General-purpose digital input/output 1. This pin is a bidirectional, digital input/output, and has an GPIO-1 8 9 I/O open-drain output. A 10k Ω pull-up resistor to IOVDD is needed when this pin is used as an output. See the GPIO Pins section for details. Output mode selection of group A (DAC-0 and DAC-1). When UNI/BIP-A is tied to IOVDD, group A is in unipolar output mode; when tied to DGND, group A is in bipolar output mode. The input data UNI/BIP-A 9 10 I written to the DAC are straight binary for unipolar output mode and twos complement for bipolar output mode. DGND 10 11 I Digital ground IOVDD 11 13 I Interface power DVDD 12 14 I Digital power VOUT-0 13 15 O DAC-0 output Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): DAC8734 |
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