DS92LV2412 Deserializer Pin Descriptions

Pin Name

Pin #

I/O, Type

Description

LVCMOS Parallel Interface

DO[7:0]

33, 34, 35,

36, 37, 39,

40, 41

I, STRAP,

O, LVCMOS

Parallel Interface Data Output Pins

For 8–bit RED Display: DO7 = R7 – MSB, DO0 = R0 – LSB.

In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 7). These

pins are inputs during power-up (See STRAP Inputs).

DO[15:8]

20, 21, 22,

23, 25, 26,

27, 28

I, STRAP,

O, LVCMOS

Parallel Interface Data Output Pins

For 8–bit GREEN Display: DO15 = G7 – MSB, DO8 = G0 – LSB.

In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 7). These

pins are inputs during power-up (See STRAP Inputs).

DO[23:16]

9, 10, 11,

12, 14, 17,

18, 19

I, STRAP,

O, LVCMOS

Parallel Interface Data Input Pins

For 8–bit BLUE Display: DO23 = B7 – MSB, DO16 = B0 – LSB.

In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 7). These

pins are inputs during power-up (See STRAP Inputs).

CO1

6

O, LVCMOS Control Signal Output

For Display/Video Application:

CO1 = Data Enable Output

Control signal pulse width must be 3 clocks or longer to be transmitted when the Control

Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition

pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).

The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter

setting.

In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 7).

CO2

8

O, LVCMOS Control Signal Output

For Display/Video Application:

CO2 = Horizontal Sync Output

Control signal pulse width must be 3 clocks or longer to be transmitted when the Control

Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition

pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).

The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter

setting.

In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 7).

CO3

7

O, LVCMOS Control Signal Output

For Display/Video Application:

CO3 = Vertical Sync Output

CO3 is different than CO1 and CO2 because it is limited to 1 transition per 130 clock cycles.

Thus, the minimum pulse width allowed is 130 clock cycle wide.

The CONFIG[1:0] pins have no affect on CO3 signal

In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 7).

CLKOUT

5

O, LVCMOS Pixel Clock Output

In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 7). Data

strobe edge set by RFB.

LOCK

32

O, LVCMOS LOCK Status Output

LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, DO[23:0], CO1,

CO2, CO3 and CLKOUT output states are controlled by OSS_SEL (See Table 7). May be

used as Link Status or to flag when Video Data is active (ON/OFF).

PASS

42

O, LVCMOS PASS Output (BIST Mode)

PASS = 1, error free transmission

PASS = 0, one or more errors were detected in the received payload

Route to test point for monitoring, or leave open if unused.

Control and Configuration — STRAP PINS

For a High State, use a 10 k

Ω pull up to V

power-up and set device configuration. Pin Number listed along with shared data output name in square brackets.

7

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