Electronic Components Datasheet Search |
|
DS92LV0421SQ Datasheet(PDF) 1 Page - National Semiconductor (TI) |
|
|
DS92LV0421SQ Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 40 page DS92LV0421 / DS92LV0422 PRELIMINARY May 26, 2010 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface General Description The DS92LV0421 (serializer) and DS92LV0422 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized inter- face over a single CML pair. The DS92LV0421 and DS92LV0422 enable applications that currently use the popular Channel Link or Channel Link style devices to seamlessly upgrade to an embedded clock inter- face to reduce interconnect cost or ease design challenges. The parallel LVDS interface also reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces. Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables longer dis- tance transmission over lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” operation. The DS92LV0421 and DS92LV0422 are programmable though an I2C interface as well as by pins. A built-in AT- SPEED BIST feature validates link integrity and may be used for system diagnostics. The DS92LV0421 and DS92LV0422 can be used inter- changeably with the DS92LV2421 or DS92LV2422. This al- lows designers the flexibility to connect to the host device and receiving devices with different interface types, LVDS or LVC- MOS. Features ■ 5-channel (4 data + 1 clock) Channel Link LVDS parallel interface supports 24-bit data 3-bit control at 10 – 75 MHz ■ AC Coupled STP Interconnect up to 10 meters in length ■ Integrated serial CML terminations ■ AT–SPEED BIST Mode and status pin ■ Optional I2C compatible Serial Control Bus ■ Power Down Mode minimizes power dissipation ■ 1.8V or 3.3V compatible control pin interface ■ >8 kV ESD (HBM) protection ■ -40° to +85°C temperature range SERIALIZER – DS92LV0421 ■ Data scrambler for reduced EMI ■ DC–balance encoder for AC coupling ■ Selectable output VOD and adjustable de-emphasis DESERIALIZER – DS92LV0422 ■ Random data lock; no reference clock required ■ Adjustable input receiver equalization ■ EMI minimization on output parallel bus (Spread Spectrum Clock Generation and LVDS VOD select) Applications ■ Embedded Video and Display ■ Machine Vision, Industrial Imaging, Medical Imaging ■ Office Automation — Printers, Scanners, Copiers ■ Security and Video Surveillance ■ General purpose data communication Applications Diagram 30120927 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation 301209 www.national.com |
Similar Part No. - DS92LV0421SQ |
|
Similar Description - DS92LV0421SQ |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |