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LTC2481 Datasheet(PDF) 5 Page - Linear Technology |
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LTC2481 Datasheet(HTML) 5 Page - Linear Technology |
5 / 40 page LTC2481 5 2481fc SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fEOSC External Oscillator Frequency Range l 10 4000 kHz tHEO External Oscillator High Period l 0.125 100 μs tLEO External Oscillator Low Period l 0.125 100 μs tCONV_1 Conversion Time for 1x Speed Mode 50Hz Mode 50Hz Mode (H-Grade) 60Hz Mode 60Hz Mode (H-Grade) Simultaneous 50Hz/60Hz Mode Simultaneous 50Hz/60Hz Mode (H-Grade) External Oscillator (Note 10) l l l l l l l 157.2 157.2 131.0 131.0 144.1 144.1 160.3 160.3 133.6 133.6 146.9 146.9 41036/fEOSC 163.5 165.1 136.3 137.6 149.9 151.0 ms ms ms ms ms ms ms tCONV_2 Conversion Time for 2x Speed Mode 50Hz Mode 50Hz Mode (H-Grade) 60Hz Mode 60Hz Mode (H-Grade) Simultaneous 50Hz/60Hz Mode Simultaneous 50Hz/60Hz Mode (H-Grade) External Oscillator (Note 10) l l l l l l l 78.7 65.6 72.2 80.3 66.9 73.6 20556/fEOSC 81.9 82.7 68.2 68.9 75.1 75.6 ms ms ms ms ms ms ms TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) I2C TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 15) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSCL SCL Clock Frequency l 0 400 kHz tHD(SDA) Hold Time (Repeated) START Condition l 0.6 μs tLOW LOW Period of the SCL Clock Pin l 1.3 μs tHIGH HIGH Period of the SCL Clock Pin l 0.6 μs tSU(STA) Set-Up Time for a Repeated START Condition l 0.6 μs tHD(DAT) Data Hold Time l 0 0.9 μs tSU(DAT) Data Set-Up Time l 100 ns tr Rise Time for Both SDA and SCL Signals (Note 14) l 20+0.1CB 300 ns tf Fall Time for Both SDA and SCL Signals (Note 14) l 20+0.1CB 300 ns tSU(STO) Set-Up Time for STOP Condition l 0.6 μs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2, FS = 0.5VREF/GAIN; VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2. Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external oscillator). Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC = 280kHz ±2% (external oscillator). Note 10: The external oscillator is connected to the CA0/f0 pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 11: The converter uses the internal oscillator. Note 12: The output noise includes the contribution of the internal calibration operations. Note 13: Guaranteed by design and test correlation. Note 14: CB = capacitance of one bus line in pF. Note 15: All values refer to VIH(MIN) and VIL(MAX) levels. |
Similar Part No. - LTC2481_1 |
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Similar Description - LTC2481_1 |
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