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LTC2453IDDB-TRPBF Datasheet(PDF) 9 Page - Linear Technology |
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LTC2453IDDB-TRPBF Datasheet(HTML) 9 Page - Linear Technology |
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9 / 18 page  LTC2453 9 2453fb Data Transferring After the START condition, the I2C bus is busy and data transfer can begin between the master and the addressed slave. Data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ACK) bit. The master releases the SDA line during the ninth SCL clock cycle. The slave device can issue an ACK by pulling SDA LOW or issue a Not Acknowledge (NAK) by leaving the SDA line HIGH impedance (the external pull-up resistor will hold the line HIGH). Change of data only occurs while the clock line (SCL) is LOW. Data Format After a START condition, the master sends a 7-bit address followed by a read request (R) bit. The bit R is 1 for a Read Request. If the 7-bit address matches the LTC2453’s address (hard-wired at 0010100) the ADC is selected. When the device is addressed during the conversion state, it does not accept the request and issues a NAK by leaving the SDA line HIGH. If the conversion is complete, the LTC2453 issues an ACK by pulling the SDA line LOW. Following the ACK, the LTC2453 can output data. The data output stream is 16 bits long and is shifted out on the falling edges of SCL (see Figure 4). The first bit output by the LTC2453, the MSB, is the sign, which is 1 for VIN+ ≥ VIN– and 0 for VIN+ < VIN– (see Table 1). The MSB (D15) is followed by successively less significant bits (D14, D13…) until the LSB is output by the LTC2453. This sequence is shown in Figure 5. OPERATION SEQUENCE Continuous Read Conversions from the LTC2453 can be continuously read, see Figure 6. At the end of a read operation, a new conversion automatically begins. At the conclusion of the conversion cycle, the next result may be read using the method described above. If the conversion cycle is not complete and a valid address selects the device, the LTC2453 generates a NAK signal indicating the conversion cycle is in progress. Discarding a Conversion Result and Initiating a New Conversion It is possible to start a new conversion without reading the old result, as shown in Figure 7. Following a valid 7-bit address, a read request (R) bit, and a valid ACK, a STOP command will start a new conversion. PRESERVING THE CONVERTER ACCURACY The LTC2453 is designed to dramatically reduce the conversion result’s sensitivity to device decoupling, PCB layout, antialiasing circuits, line and frequency perturbations. Nevertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels Due to the nature of CMOS logic, it is advisable to keep input digital signals near GND or VCC. Voltages in the range of 0.5V to VCC – 0.5V may result in additional current leakage from the part. SDA SCL SSr P S tHD(STA) tHD(DAT) tSU(STA) tSU(STO) tSU(DAT) tLOW tHD(SDA) tSP tBUF tr tf tr tf tHIGH 2453 F03 Figure 3. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus APPLICATIONS INFORMATION |
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