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INT202PFI1 Datasheet(PDF) 4 Page - Power Integrations, Inc. |
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INT202PFI1 Datasheet(HTML) 4 Page - Power Integrations, Inc. |
4 / 12 page INT202 F 2/96 4 4 General Circuit Operation The three-phase switched reluctance motor drive circuit shown in Figure 4 illustrates a typical application for the INT202/201. The LS IN signal directly controls MOSFET Q1. The HSINsignal causes the INT202 to command the INT201 to turn MOSFET Q2 on or off as required. Local bypassing for the low-side driver is provided by C1. Bootstrap bias for the high-side driver is provided by D1 and C2. Slew rate and effects of parasitic oscillations in the load waveforms are controlled by resistors R1 and R2. The inputs are designed to be compatible with 5 V CMOS logic levels and should not be connected to V DD. Normal CMOS power supply sequencing should be observed. The order of signal application should be V DD, logic signals, and then HV+. V DD should be supplied from a low impedance voltage source. The length of time that the high-side can remain on is limited by the size of the bootstrap capacitor. Applications with extremely long high-side on times require special techniques discussed in AN-10. Maximum frequency of operation is limited by power dissipation due to high- voltage switching, gate charge, and bias power. Figure 5 indicates the maximum switching frequency as a function of input voltage and gate charge. For higher ambient temperatures, the switching frequency should be derated linearly. Figure 5. Switching Frequency versus Gate Charge for a) PDIP and b) SOIC. 100 0 0 100 200 Gate Charge (nC) 200 300 400 VIN = 200 V VIN = 300 V VIN = 400 V PDIP 100 0 0 100 200 Gate Charge (nC) 200 300 400 VIN = 200 V VIN = 300 V VIN = 400 V SOIC |
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