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PIC12F519 Datasheet(PDF) 11 Page - Microchip Technology |
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PIC12F519 Datasheet(HTML) 11 Page - Microchip Technology |
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11 / 96 page  © 2008 Microchip Technology Inc. DS41319B-page 9 PIC12F519 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC12F519 device can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12F519 device uses a Harvard architec- ture in which program and data are accessed on sep- arate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instruc- tions (33) execute in a single cycle (500 ns @ 8 MHz, 1 μs @ 4 MHz) except for program branches. Table 3-1 below lists memory supported by the PIC12F519 device. TABLE 3-1: PIC12F519 MEMORY The PIC12F519 device can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC12F519 device has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. This symmet- rical nature and lack of “special optimal situations” make programming with the PIC12F519 device simple, yet efficient. In addition, the learning curve is reduced significantly. The PIC12F519 device contains an 8-bit ALU and working register. The ALU is a general purpose arith- metic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless other- wise mentioned, arithmetic operations are two’s complement in nature. In two-operand instructions, one operand is typically the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respec- tively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-2. Device Program Memory Data Memory Flash (words) SRAM (bytes) Flash Data (bytes) PIC12F519 1024 41 64 |
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