 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
R2J20651ANP Datasheet(PDF) 4 Page - Renesas Technology Corp |
|
||||||||||||||||||||||||||||||
R2J20651ANP Datasheet(HTML) 4 Page - Renesas Technology Corp |
|
|
4 / 20 page  R2J20651ANP Preliminary REJ03G1792-0200 Rev.2.00 Mar 12, 2010 Page 2 of 17 Block Diagram BOOT GH VIN GL VDRV PGND VSWH CGND PWM LSDBL# DISBL# THWN VCIN Driver chip High-side MOS FET Low-side MOS FET 0.5 μA CGND CGND VCIN VCIN 20 μA Level shifter SBD 150 k 25 k Input logic (TTL level) (3 state in) THWN Overlap protection UVL Notes: 1. Truth table for the DISBL# pin. 2. Truth table for the LSDBL# pin. DISBL# Input Driver Chip Status "L" Shutdown (GL, GH = "L") "Open" Shutdown (GL, GH = "L") "H" Enable (GL, GH = "Active") LSDBL# Input GL Status "L" "L" "Open" "Active" "H" "Active" 3. Output signal from the UVL block 4. Output signal from the THWN block For active UVL Output Logic Level For shutdown "H" VL VCIN VH "L" Thermal warning THWN Output Logic Level Normal operating "H" TL TIC (°C) TH "L" |
Similar Part No. - R2J20651ANP_10 |
|
Similar Description - R2J20651ANP_10 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
