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I.MX27 Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc |
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I.MX27 Datasheet(HTML) 67 Page - Freescale Semiconductor, Inc |
67 / 148 page i.MX27 and i.MX27L Data Sheet, Rev. 1.5 Freescale Semiconductor 67 Electrical Characteristics 4.3.7 NAND Flash Controller Interface (NFC) Figure 31, Figure 32, Figure 33, and Figure 34 show the relative timing requirements among different signals of the NFC at module level, and Table 35 lists the timing parameters. The NAND Flash Controller (NFC) timing parameters are based on the internal NFC clock generated by the Clock Controller module, where time T is the period of the NFC clock in ns. The relationship between the NFC clock and the external timing parameters of the NFC is provided in Table 35. Table 35 also provides two examples of external timing parameters with NFC clock frequencies of 22.17 MHz and 33.25 MHz. Assuming a 266 MHz FCLK (CPU clock), NFCDIV should be set to divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC clock. The user should compare the parameters of the selected NAND Flash memory with the NFC external timing parameters to determine the proper NFC clock. The maximum NFC clock allowed is 66 MHz. It should also be noted that the default NFC clock on power up is 16.63 MHz. MSHC_BS Setup time tBSsu 5 — ns Hold time tBSh 5 — ns MSHC_DATA Setup time tDsu 5 — ns Hold time tDh 5 — ns Output delay time tDd — 15 ns Table 34. Parallel Interface Timing Parameters Signal Parameter Symbol Standards Unit Min Max MSHC_SCLK Cycle tSCLKc 25 — ns H pulse length tSCLKwh 5 — ns L pulse length tSCLKwl 5 — ns Rise time tSCLKr — 10 ns Fall time tSCLKf — 10 ns MSHC_BS Setup time tBSsu 8 — ns Hold time tBSh 1 — ns MSHC_DATA Setup time tDsu 8 — ns Hold time tDh 1 — ns Output delay time tDd — 15 ns Table 33. Serial Interface Timing Parameters (continued) Signal Parameter Symbol Standards Unit Min. Max. |
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