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PIC18LF26J53 Datasheet(PDF) 94 Page - Microchip Technology

Part No. PIC18LF26J53
Description  28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology
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Maker  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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PIC18LF26J53 Datasheet(HTML) 94 Page - Microchip Technology

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PIC18F47J53 FAMILY
DS39964B-page 94
Preliminary
 2010 Microchip Technology Inc.
6.3.5.1
Context Defined SFRs
There are several registers that share the same
address in the SFR space. The register's definition and
usage depends on the operating mode of its associated
peripheral. These registers are:
• SSPxADD and SSPxMSK: These are two
separate hardware registers, accessed through a
single SFR address. The operating mode of the
MSSP modules determines which register is
being accessed. See Section 20.5.3.4 “7-Bit
Address Masking Mode” for additional details.
• PMADDRH/L and PMDOUT2H/L: In this case,
these named buffer pairs are actually the same
physical registers. The Parallel Master Port (PMP)
module’s operating mode determines what func-
tion the registers take on. See Section 11.1.2
“Data Registers” for additional details.
TABLE 6-4:
REGISTER FILE SUMMARY (PIC18F47J53 FAMILY)
Addr.
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
FFFh
TOSU
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
FFEh
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
FFDh
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
FFCh
STKPTR
STKFUL
STKUNF
SP4
SP3
SP2
SP1
SP0
00-0 0000
FFBh
PCLATU
bit 21
Holding Register for PC<20:16>
---0 0000
FFAh
PCLATH
Holding Register for PC<15:8>
0000 0000
FF9h
PCL
PC Low Byte (PC<7:0>)
0000 0000
FF8h
TBLPTRU
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
FF7h
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
FF6h
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
FF5h
TABLAT
Program Memory Table Latch
0000 0000
FF4h
PRODH
Product Register High Byte
xxxx xxxx
FF3h
PRODL
Product Register Low Byte
xxxx xxxx
FF2h
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
FF1h
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
1111 1111
FF0h
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
1100 0000
FEFh
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
FEEh
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
FEDh
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
FECh
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
FEBh
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
FEAh
FSR0H
Indirect Data Memory Address Pointer 0 High Byte
---- xxxx
FE9h
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
FE8h
WREG
Working Register
xxxx xxxx
FE7h
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
FE6h
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
FE5h
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
FE4h
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
FE3h
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FE2h
FSR1H
Indirect Data Memory Address Pointer 1 High Byte
---- xxxx
FE1h
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
FE0h
BSR
Bank Select Register
---- 0000
FDFh
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
FDEh
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
FDDh
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
Legend:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1:
Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
2:
Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
3:
Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53).


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