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PIC18LF26J53 Datasheet(PDF) 92 Page - Microchip Technology

Part No. PIC18LF26J53
Description  28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology
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Maker  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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PIC18LF26J53 Datasheet(HTML) 92 Page - Microchip Technology

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PIC18F47J53 FAMILY
DS39964B-page 92
Preliminary
 2010 Microchip Technology Inc.
6.3.5
SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and periph-
eral modules for controlling the desired operation of the
device. These registers are implemented as static
RAM. SFRs start at the top of data memory (FFFh) and
extend downward to occupy more than the top half of
Bank 15 (F40h to FFFh). Table 6-2, Table 6-3 and
Table 6-4 provide a list of these registers.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their corresponding chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
Note:
The SFRs located between EB0h and
F5Fh are not part of the Access Bank.
Either BANKED instructions (using BSR) or
the MOVFF instruction should be used to
access these locations. When program-
ming in MPLAB® C18, the compiler will
automatically
use
the
appropriate
addressing mode.
TABLE 6-2:
ACCESS BANK SPECIAL FUNCTION REGISTER MAP
Address
Name
Address
Name
Address
Name
Address
Name
Address
Name
FFFh
TOSU
FDFh
INDF2(1)
FBFh
PSTR1CON
F9Fh
IPR1
F7Fh
SPBRGH1
FFEh
TOSH
FDEh
POSTINC2(1)
FBEh
ECCP1AS
F9Eh
PIR1
F7Eh
BAUDCON1
FFDh
TOSL
FDDh
POSTDEC2(1)
FBDh
ECCP1DEL
F9Dh
PIE1
F7Dh
SPBRGH2
FFCh
STKPTR
FDCh
PREINC2(1)
FBCh
CCPR1H
F9Ch
RCSTA2
F7Ch
BAUDCON2
FFBh
PCLATU
FDBh
PLUSW2(1)
FBBh
CCPR1L
F9Bh
OSCTUNE
F7Bh
TMR3H
FFAh
PCLATH
FDAh
FSR2H
FBAh
CCP1CON
F9Ah
T1GCON
F7Ah
TMR3L
FF9h
PCL
FD9h
FSR2L
FB9h
PSTR2CON
F99h
IPR5
F79h
T3CON
FF8h
TBLPTRU
FD8h
STATUS
FB8h
ECCP2AS
F98h
PIR5
F78h
TMR4
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
ECCP2DEL
F97h
T3GCON
F77h
PR4
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
CCPR2H
F96h
TRISE
F76h
T4CON
FF5h
TABLAT
FD5h
T0CON
FB5h
CCPR2L
F95h
TRISD
F75h
SSP2BUF
FF4h
PRODH
FD4h
(5)
FB4h
CCP2CON
F94h
TRISC
F74h
SSP2ADD(3)
FF3h
PRODL
FD3h
OSCCON
FB3h CTMUCONH
F93h
TRISB
F73h
SSP2STAT
FF2h
INTCON
FD2h
CM1CON
FB2h CTMUCONL
F92h
TRISA
F72h
SSP2CON1
FF1h
INTCON2
FD1h
CM2CON
FB1h
CTMUICON
F91h
PIE5
F71h
SSP2CON2
FF0h
INTCON3
FD0h
RCON
FB0h
SPBRG1
F90h
IPR4
F70h
CMSTAT
FEFh
INDF0(1)
FCFh
TMR1H
FAFh
RCREG1
F8Fh
PIR4
F6Fh
PMADDRH(2,4)
FEEh
POSTINC0(1)
FCEh
TMR1L
FAEh
TXREG1
F8Eh
PIE4
F6Eh
PMADDRL(2,4)
FEDh
POSTDEC0(1)
FCDh
T1CON
FADh
TXSTA1
F8Dh
LATE(2)
F6Dh
PMDIN1H(2)
FECh
PREINC0(1)
FCCh
TMR2
FACh
RCSTA1
F8Ch
LATD(2)
F6Ch
PMDIN1L(2)
FEBh
PLUSW0(1)
FCBh
PR2
FABh
SPBRG2
F8Bh
LATC
F6Bh
TXADDRL
FEAh
FSR0H
FCAh
T2CON
FAAh
RCREG2
F8Ah
LATB
F6Ah
TXADDRH
FE9h
FSR0L
FC9h
SSP1BUF
FA9h
TXREG2
F89h
LATA
F69h
RXADDRL
FE8h
WREG
FC8h
SSP1ADD(3)
FA8h
TXSTA2
F88h
DMACON1
F68h
RXADDRH
FE7h
INDF1(1)
FC7h
SSP1STAT
FA7h
EECON2
F87h
OSCCON2(5)
F67h
DMABCL
FE6h
POSTINC1(1)
FC6h
SSP1CON1
FA6h
EECON1
F86h
DMACON2
F66h
DMABCH
FE5h
POSTDEC1(1)
FC5h
SSP1CON2
FA5h
IPR3
F85h
HLVDCON
F65h
UCON
FE4h
PREINC1(1)
FC4h
ADRESH
FA4h
PIR3
F84h
PORTE(2)
F64h
USTAT
FE3h
PLUSW1(1)
FC3h
ADRESL
FA3h
PIE3
F83h
PORTD(2)
F63h
UEIR
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
F62h
UIR
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
F61h
UFRMH
FE0h
BSR
FC0h
WDTCON
FA0h
PIE2
F80h
PORTA
F60h
UFRML
Note 1:
This is not a physical register.
2:
This register is not available on 28-pin devices.
3:
SSPxADD and SSPxMSK share the same address.
4:
PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address.
PMADDRx is used in Master modes and PMDOUTx is used in Slave modes.
5:
Reserved: Do not write to this location.


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