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PIC18LF26J53 Datasheet(PDF) 88 Page - Microchip Technology |
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PIC18LF26J53 Datasheet(HTML) 88 Page - Microchip Technology |
88 / 586 page PIC18F47J53 FAMILY DS39964B-page 88 Preliminary 2010 Microchip Technology Inc. 6.3 Data Memory Organization The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each. The PIC18F47J53 family implements all available banks and provides 3.8 Kbytes of data memory available to the user. Figure 6-6 provides the data memory organization for the devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s application. Any read of an unimplemented location will read as ‘0’s. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this section. To ensure that commonly used registers (select SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to select SFRs and the lower portion of GPR Bank 0 with- out using the BSR. Section 6.3.3 “Access Bank” provides a detailed description of the Access RAM. 6.3.1 USB RAM All 3.8 Kbytes of the GPRs implemented on the PIC18F47J53 family devices can be accessed simulta- neously by both the microcontroller core and the Serial Interface Engine (SIE) of the USB module. The SIE uses a dedicated USB DMA engine to store any incoming data packets (OUT/SETUP) directly into the main system data memory. For IN data packets, the SIE can directly read the contents of general purpose SRAM and uses it to create USB data packets that are sent to the host. SRAM Bank 13 (D00h-DFFh) is unique. In addition to being accessible by both the microcontroller core and the USB module, the SIE uses a portion of Bank 13 as Special Function Registers (SFRs). These SFRs compose the Buffer Descriptor Table (BDT). When the USB module is enabled, the BDT registers are used to control the behavior of the USB DMA oper- ation for each of the enabled endpoints. The exact number of SRAM locations that are used for the BDT depends on how many endpoints are enabled and what USB Ping-Pong mode is used. For more details, see Section 23.3 “USB RAM”. When the USB module is disabled, these SRAM loca- tions behave like any other GPR location. When the USB module is disabled, these locations may be used for any general purpose. Note: The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. Note: IN and OUT are always from the USB host's perspective. |
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