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PIC18LF26J53 Datasheet(PDF) 85 Page - Microchip Technology |
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PIC18LF26J53 Datasheet(HTML) 85 Page - Microchip Technology |
85 / 586 page 2010 Microchip Technology Inc. Preliminary DS39964B-page 85 PIC18F47J53 FAMILY 6.1.4.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration register 1L. When STVREN is set, a full or underflow condition sets the appropriate STKFUL or STKUNF bit and then causes a device Reset. When STVREN is cleared, a full or underflow condition sets the appropriate STKFUL or STKUNF bit, but does not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a POR. 6.1.5 FAST REGISTER STACK (FRS) A Fast Register Stack (FRS) is provided for the STATUS, WREG and BSR registers to provide a “fast return” option for interrupts. This stack is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All inter- rupt sources push values into the Stack registers. The values in the registers are then loaded back into the working registers if the RETFIE, FAST instruction is used to return from the interrupt. If both low-priority and high-priority interrupts are enabled, the Stack registers cannot be used reliably to return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the Stack register values stored by the low-priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the FRS for returns from interrupt. If no interrupts are used, the FRS can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the FRS. Example 6-1 provides a source code example that uses the FRS during a subroutine call and return. EXAMPLE 6-1: FAST REGISTER STACK CODE EXAMPLE 6.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures or look-up tables in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • Computed GOTO • Table Reads 6.1.6.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the PC. An example is shown in Example 6-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next executed instruction will be one of the RETLW nn instructions that returns the value, ‘nn’, to the calling function. The offset value (in WREG) specifies the number of bytes that the PC should advance and should be multiples of 2 (LSb = 0). In this method, only one byte may be stored in each instruction location, but room on the return address stack is required. EXAMPLE 6-2: COMPUTED GOTO USING AN OFFSET VALUE 6.1.6.2 Table Reads A better method of storing data in program memory allows two bytes to be stored in each instruction location. Look-up table data may be stored two bytes per program word while programming. The Table Pointer (TBLPTR) specifies the byte address, and the Table Latch (TABLAT) contains the data that is read from the program memory. Data is transferred from program memory, one byte at a time. Table read operation is discussed further in Section 7.1 “Table Reads and Table Writes”. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK MOVF OFFSET, W CALL TABLE ORG nn00h TABLE ADDWF PCL RETLW nnh RETLW nnh RETLW nnh . . . |
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