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PIC18LF26J53 Datasheet(PDF) 82 Page - Microchip Technology

Part No. PIC18LF26J53
Description  28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology
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Maker  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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PIC18LF26J53 Datasheet(HTML) 82 Page - Microchip Technology

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PIC18F47J53 FAMILY
DS39964B-page 82
Preliminary
 2010 Microchip Technology Inc.
6.1.1
HARD MEMORY VECTORS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
program counter returns on all device Resets; it is
located at 0000h.
PIC18 devices also have two interrupt vector
addresses for handling high-priority and low-priority
interrupts. The high-priority interrupt vector is located at
0008h and the low-priority interrupt vector at 0018h.
Figure 6-2 provides their locations in relation to the
program memory map.
FIGURE 6-2:
HARD VECTOR AND
CONFIGURATION WORD
LOCATIONS FOR
PIC18F47J53 FAMILY
DEVICES
6.1.2
FLASH CONFIGURATION WORDS
Because PIC18F47J53 family devices do not have
persistent configuration memory, the top four words of
on-chip program memory are reserved for configuration
information. On Reset, the configuration information is
copied into the Configuration registers.
The Configuration Words are stored in their program
memory location in numerical order, starting with the
lower byte of CONFIG1 at the lowest address and
ending with the upper byte of CONFIG4.
Table 6-1 provides the actual addresses of the Flash
Configuration Word for devices in the PIC18F47J53
family. Figure 6-2 displays their location in the memory
map with other memory vectors.
Additional details on the device Configuration Words
are provided in Section 28.1 “Configuration Bits”.
TABLE 6-1:
FLASH CONFIGURATION
WORD FOR PIC18F47J53
FAMILY DEVICES
Reset Vector
Low-Priority Interrupt Vector
0000h
0018h
On-Chip
Program Memory
High-Priority Interrupt Vector
0008h
1FFFFFh
(Top of Memory)
(Top of Memory-7)
Flash Configuration Words
Read as ‘0’
Legend:
(Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 6-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
Device
Program
Memory
(Kbytes)
Configuration
Word Addresses
PIC18F26J53
64
FFF8h to FFFFh
PIC18F46J53
PIC18F27J53
128
1FFF8h to 1FFFFh
PIC18F47J53


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