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PIC18LF26J53 Datasheet(PDF) 65 Page - Microchip Technology |
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PIC18LF26J53 Datasheet(HTML) 65 Page - Microchip Technology |
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65 / 586 page  2010 Microchip Technology Inc. Preliminary DS39964B-page 65 PIC18F47J53 FAMILY 5.0 RESET The PIC18F47J53 family of devices differentiates among various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Configuration Mismatch (CM) f) Brown-out Reset (BOR) g) RESET Instruction h) Stack Full Reset i) Stack Underflow Reset j) Deep Sleep Reset This section discusses Resets generated by MCLR, POR and BOR, and covers the operation of the various start-up timers. For information on WDT Resets, see Section 28.2 “Watchdog Timer (WDT)”. For Stack Reset events, see Section 6.1.4.4 “Stack Full and Underflow Resets” and for Deep Sleep mode, see Section 4.6 “Deep Sleep Mode”. Figure 5-1 provides a simplified block diagram of the on-chip Reset circuit. 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be set by the event and must be cleared by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 5.7 “Reset State of Registers”. The RCON register also has a control bit for setting interrupt priority (IPEN). Interrupt priority is discussed in Section 9.0 “Interrupts”. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR VDD WDT Time-out VDD Rise Detect PWRT INTRC POR Pulse Chip_Reset Brown-out Reset(1) RESET Instruction Stack Pointer Stack Full/Underflow Reset Sleep ( )_IDLE 32 ms PWRT 11-Bit Ripple Counter 66 ms S RQ Configuration Word Mismatch Deep Sleep Reset Note 1: The VDD monitoring BOR circuit can be enabled or disabled on “LF” devices based on the CONFIG3L<DSBOREN> Configuration bit. On “F” devices, the VDD monitoring BOR circuit is only enabled during Deep Sleep mode by CONFIG3L<DSBOREN>. 2: The VDDCORE monitoring BOR circuit is only implemented on “F” devices. It is always used, except while in Deep Sleep mode. The VDDCORE monitoring BOR circuit has a trip point threshold of VBOR (parameter D005). VDDCORE Brown-out Reset(2) |
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