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PIC18LF26J53 Datasheet(PDF) 58 Page - Microchip Technology |
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PIC18LF26J53 Datasheet(HTML) 58 Page - Microchip Technology |
58 / 586 page PIC18F47J53 FAMILY DS39964B-page 58 Preliminary 2010 Microchip Technology Inc. 4.6.9 DEEP SLEEP MODE REGISTERS Deep Sleep mode registers are provided in Register 4-1 through Register 4-6. REGISTER 4-1: DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh) R/W-0 U-0 U-0 U-0 U-0 r-0 R/W-0 R/W-0 DSEN(1) — — — — r DSULPEN RTCWDIS bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DSEN: Deep Sleep Enable bit(1) 1 = Deep Sleep mode is entered on a SLEEP command 0 = Sleep mode is entered on a SLEEP command bit 6-3 Unimplemented: Read as ‘0’ bit 2 (Reserved): Always write ‘0’ to this bit bit 1 DSULPEN: Ultra Low-Power Wake-up Module Enable bit 1 = ULPWU module is enabled in Deep Sleep 0 = ULPWU module is disabled in Deep Sleep bit 0 RTCWDIS: RTCC Wake-up Disable bit 1 = Wake-up from RTCC is disabled 0 = Wake-up from RTCC is enabled Note 1: In order to enter Deep Sleep, Sleep must be executed immediately after setting DSEN. REGISTER 4-2: DSCONL: DEEP SLEEP LOW BYTE CONTROL REGISTER (BANKED F4Ch) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0(1) R/W-0(1) — — — — — ULPWDIS DSBOR RELEASE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 ULPWDIS: Ultra Low-Power Wake-up Disable bit 1 = ULPWU wake-up source is disabled 0 = ULPWU wake-up source is enabled (must also set DSULPEN = 1) bit 1 DSBOR: Deep Sleep BOR Event Status bit 1 = DSBOREN was enabled and VDD dropped below the DSBOR arming voltage during Deep Sleep, but did not fall below VDSBOR 0 = DSBOREN was disabled or VDD did not drop below the DSBOR arming voltage during Deep Sleep bit 0 RELEASE: I/O Pin State Release bit Upon waking from Deep Sleep, the I/O pins maintain their previous states. Clearing this bit will release the I/O pins and allow their respective TRIS and LAT bits to control their states. Note 1: This is the value when VDD is initially applied. |
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