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PIC18LF26J53 Datasheet(PDF) 57 Page - Microchip Technology

Part No. PIC18LF26J53
Description  28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology
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Maker  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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PIC18LF26J53 Datasheet(HTML) 57 Page - Microchip Technology

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 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 57
PIC18F47J53 FAMILY
4.6.5
DEEP SLEEP BROWN-OUT RESET
(DSBOR)
The Deep Sleep module contains a dedicated Deep Sleep
BOR (DSBOR) circuit. This circuit may be optionally
enabled through the DSBOREN Configuration bit.
The DSBOR circuit monitors the VDD supply rail
voltage. The behavior of the DSBOR circuit is
described in Section 5.4 “Brown-out Reset (BOR)”.
4.6.6
RTCC PERIPHERAL AND DEEP
SLEEP
The RTCC can operate uninterrupted during Deep
Sleep mode. It can wake the device from Deep Sleep
by configuring an alarm.
The RTCC clock source is configured with the
RTCOSC bit (CONFIG3L<1>). The available reference
clock sources are the INTRC and T1OSC/T1CKI. If the
INTRC is used, the RTCC accuracy will directly depend
on the INTRC tolerance.For more information on
configuring the RTCC peripheral, see Section 17.0
“Real-Time Clock and Calendar (RTCC)”.
4.6.7
TYPICAL DEEP SLEEP SEQUENCE
This section gives the typical sequence for using the Deep
Sleep mode. Optional steps are indicated and additional
information is given in notes at the end of the procedure.
1.
Enable DSWDT (optional).(1)
2.
Configure the DSWDT clock source (optional).(2)
3.
Enable DSBOR (optional).(1)
4.
Enable RTCC (optional).(3)
5.
Configure the RTCC peripheral (optional).(3)
6.
Configure the ULPWU peripheral (optional).(4)
7.
Enable the INT0 Interrupt (optional).
8.
Context save SRAM data by writing to the
DSGPR0 and DSGPR1 registers (optional).
9.
Set the REGSLP bit (WDTCON<7>) and clear
the IDLEN bit (OSCCON<7>).
10. If using an RTCC alarm for wake-up, wait until
the RTCSYNC bit (RTCCFG<4>) is clear.
11. Enter Deep Sleep mode by setting the DSEN bit
(DSCONH<7>) and issuing a SLEEP instruction.
These two instructions must be executed back
to back.
12. Once a wake-up event occurs, the device will
perform a POR Reset sequence. Code execution
resumes at the device’s Reset vector.
13. Determine if the device exited Deep Sleep by
reading the Deep Sleep bit, DS (WDTCON<3>).
This bit will be set if there was an exit from Deep
Sleep mode.
14. Clear the Deep Sleep bit, DS (WDTCON<3>).
15. Determine the wake-up source by reading the
DSWAKEH and DSWAKEL registers.
16. Determine if a DSBOR event occurred during
Deep Sleep mode by reading the DSBOR bit
(DSCONL<1>).
17. Read the DSGPR0 and DSGPR1 context save
registers (optional).
18. Clear the RELEASE bit (DSCONL<0>).
4.6.8
DEEP SLEEP FAULT DETECTION
If during Deep Sleep, the device is subjected to
unusual operating conditions, such as an Electrostatic
Discharge (ESD) event, it is possible that internal cir-
cuit states used by the Deep Sleep module could
become corrupted. If this were to happen, the device
may exhibit unexpected behavior, such as a failure to
wake back up.
In order to prevent this type of scenario from occurring,
the
Deep
Sleep
module
includes
automatic
self-monitoring capability. During Deep Sleep, critical
internal nodes are continuously monitored in order to
detect possible Fault conditions (which would not
ordinarily occur). If a Fault condition is detected, the
circuitry will set the DSFLT status bit (DSWAKEL<7>)
and automatically wake the microcontroller from Deep
Sleep, causing a POR Reset.
During Deep Sleep, the Fault detection circuitry is
always enabled and does not require any specific
configuration prior to entering Deep Sleep.
Note 1: DSWDT and DSBOR are enabled
through the devices’ Configuration bits.
For more information, see Section 28.1
“Configuration Bits”.
2: The DSWDT and RTCC clock sources
are selected through the devices’ Con-
figuration bits. For more information, see
Section 28.1 “Configuration Bits”.
3: For more information, see Section 17.0
“Real-Time
Clock
and
Calendar
(RTCC)”.
4: For more information on configuring this
peripheral,
see
Section 4.7
“Ultra
Low-Power Wake-up”.


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