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PIC18LF26J53 Datasheet(PDF) 51 Page - Microchip Technology

Part No. PIC18LF26J53
Description  28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology
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Maker  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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PIC18LF26J53 Datasheet(HTML) 51 Page - Microchip Technology

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 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 51
PIC18F47J53 FAMILY
4.3
Sleep Mode
The power-managed Sleep mode is identical to the
legacy Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 4-5). All
clock source status bits are cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep mode. If
the WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 4-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the FSCM is enabled (see Section 28.0
“Special Features of the CPU”). In either case, the
OSTS bit is set when the primary clock is providing the
device clocks. The IDLEN and SCS bits are not
affected by the wake-up.
FIGURE 4-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
FIGURE 4-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q4
Q3
Q2
OSC1
Peripheral
Sleep
Program
Q1
Q1
Counter
Clock
CPU
Clock
PC + 2
PC
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program
PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1
Q2 Q3 Q4 Q1 Q2
Clock
Counter
PC + 6
PC + 4
Q1 Q2 Q3 Q4
Wake Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1)
TPLL(1)
OSTS Bit Set
PC + 2


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