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PIC18LF26J53 Datasheet(PDF) 50 Page - Microchip Technology |
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PIC18LF26J53 Datasheet(HTML) 50 Page - Microchip Technology |
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50 / 586 page 
PIC18F47J53 FAMILY DS39964B-page 50 Preliminary 2010 Microchip Technology Inc. 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications, which are not highly timing-sensitive or do not require high-speed clocks at all times. This mode is entered by setting the SCS<1:0> bits (OSCCON<1:0>) to ‘11’. When the clock source is switched to the internal oscillator block (see Figure 4-3), the primary oscillator is shut down and the OSTS bit is cleared. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC block while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC clock source will continue to run if either the WDT or the FSCM is enabled. FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q4 Q3 Q2 OSC1 Peripheral Program Q1 INTRC Q1 Counter Clock CPU Clock PC + 2 PC 123 n-1 n Clock Transition Q4 Q3 Q2 Q1 Q3 Q2 PC + 4 Q1 Q3 Q4 OSC1 Peripheral Program PC INTRC PLL Clock Q1 PC + 4 Q2 Output Q3 Q4 Q1 CPU Clock PC + 2 Clock Counter Q2 Q2 Q3 Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. SCS<1:0> Bits Changed TPLL(1) 12 n-1 n Clock OSTS Bit Set Transition TOST(1) |
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