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PIC18LF26J53 Datasheet(PDF) 43 Page - Microchip Technology |
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PIC18LF26J53 Datasheet(HTML) 43 Page - Microchip Technology |
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43 / 586 page  2010 Microchip Technology Inc. Preliminary DS39964B-page 43 PIC18F47J53 FAMILY The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 4.0 “Low-Power Modes”. 3.5.2 OSCILLATOR TRANSITIONS PIC18F47J53 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in more detail in Section 4.1.2 “Entering Power-Managed Modes”. Note 1: The Timer1 crystal driver is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select the Timer1 clock source will be ignored, unless the CONFIG2L register’s T1DIG bit is set. 2: If Timer1 is driving a crystal, it is recom- mended that the Timer1 oscillator be operating and stable prior to switching to it as the clock source; otherwise, a very long delay may occur while the Timer1 oscillator starts. REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER (ACCESS FD3h) R/W-0 R/W-1 R/W-1 R/W-0 R-1(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS FLTS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8 MHz (INTOSC drives clock directly) 110 = 4 MHz(2) 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (from either INTOSC/256 or INTRC directly)(3) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready bit 2 FLTS: Frequency Lock Tuning Status bit 1 = INTOSC is stable 0 = INTOSC is not stable bit 1-0 SCS<1:0>: System Clock Select bits 11 = Postscaled internal clock (INTRC/INTOSC derived) 10 = Reserved 01 = Timer1 oscillator 00 = Primary clock source (INTOSC postscaler output when FOSC<2:0> = 001 or 000) 00 = Primary clock source (CPU divider output for other values of FOSC<2:0>) Note 1: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. 2: Default output frequency of INTOSC on Reset (4 MHz). 3: Source selected by the INTSRC bit (OSCTUNE<7>). |
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