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PIC18LF26J53 Datasheet(PDF) 40 Page - Microchip Technology

Part No. PIC18LF26J53
Description  28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology
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Maker  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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PIC18LF26J53 Datasheet(HTML) 40 Page - Microchip Technology

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PIC18F47J53 FAMILY
DS39964B-page 40
Preliminary
 2010 Microchip Technology Inc.
3.3
Oscillator Settings for USB
When the PIC18F47J53 family devices are used for
USB connectivity, a 6 MHz or 48 MHz clock must be
provided to the USB module for operation in either
Low-Speed or Full-Speed modes, respectively. This
may require some forethought in selecting an oscillator
frequency and programming the device.
The full range of possible oscillator configurations
compatible with USB operation is shown in Table 3-5.
3.3.1
LOW-SPEED OPERATION
The USB clock for Low-Speed mode is derived from the
primary oscillator or from the 96 MHz PLL. In order to
operate the USB module in Low-Speed mode, a 6 MHz
clock must be provided to the USB module.
See Table 3-4 and Table 3-5 for possible combinations
which can be used for low-speed USB operation.
TABLE 3-4:
CLOCK FOR LOW-SPEED USB
REGISTER 3-1:
OSCTUNE: OSCILLATOR TUNING REGISTER (ACCESS F9Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTSRC
PLLEN(1)
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
bit 6
PLLEN: Frequency Multiplier Enable bit(1)
1 = 96 MHz PLL is enabled
0 = 96 MHz PLL is disabled
bit 5-0
TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110
000001
000000 = Center frequency; oscillator module is running at the calibrated frequency
111111
100000 = Minimum frequency
Note 1:
When the CFGPLLEN Configuration bit is used to enable the PLL, clearing OSCTUNE<6> will not disable
the PLL.
System Clock
CPDIV<1:0>
Microcontroller Clock
LS48MHZ
USB Clock
48
11
48 MHz
1
48/8 = 6 MHz
48
10
48/2 = 24 MHz
1
48/8 = 6 MHz
48
01
48/3 = 16 MHz
1
48/8 = 6 MHz
48
00
48/6 = 8 MHz
1
48/8 = 6 MHz
24
11
24 MHz
0
24/4 = 6 MHz
24
10
24/2 = 12 MHz
0
24/4 = 6 MHz
24
01
24/3 = 8 MHz
0
24/4 = 6 MHz
24
00
24/6 = 4 MHz
0
24/4 = 6 MHz


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