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PIC18LF26J53 Datasheet(PDF) 39 Page - Microchip Technology |
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PIC18LF26J53 Datasheet(HTML) 39 Page - Microchip Technology |
39 / 586 page 2010 Microchip Technology Inc. Preliminary DS39964B-page 39 PIC18F47J53 FAMILY 3.2.5.1 OSCTUNE Register The internal oscillator’s output has been calibrated at the factory but can be adjusted in the user’s applica- tion. This is done by writing to the OSCTUNE register (Register 3-1). The tuning sensitivity is constant throughout the tuning range. When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. The INTOSC clock will stabilize typically within 1 s. Code execution continues during this shift. There is no indication that the shift has occurred. The OSCTUNE register also contains the INTSRC bit. The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31 kHz frequency option is selected. This is covered in larger detail in Section 3.5.1 “Oscillator Control Register”. The PLLEN bit, contained in the OSCTUNE register, can be used to enable or disable the internal 96 MHz PLL when running in one of the PLL type oscillator modes (e.g., INTOSCPLL). Oscillator modes that do not contain “PLL” in their name cannot be used with the PLL. In these modes, the PLL is always disabled regardless of the setting of the PLLEN bit. When configured for one of the PLL enabled modes, set- ting the PLLEN bit does not immediately switch the device clock to the PLL output. The PLL requires up to electrical parameter, trc, to start-up and lock, during which time, the device continues to be clocked. Once the PLL output is ready, the microcontroller core will automatically switch to the PLL derived frequency. 3.2.5.2 Internal Oscillator Output Frequency and Drift The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. However, this frequency may drift as VDD or tempera- ture changes, which can affect the controller operation in a variety of ways. The low-frequency INTRC oscillator operates indepen- dently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. 3.2.5.3 Compensating for INTOSC Drift It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency. Tuning the INTOSC source requires knowing when to make the adjustment, in which direction it should be made and in some cases, how large a change is needed. When using the EUSART, for example, an adjustment may be required when it begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high; to adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may sug- gest that the clock speed is too low; to compensate, increment OSCTUNE to increase the clock frequency. It is also possible to verify device clock speed against a reference clock. Two timers may be used: one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. Finally, an ECCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is greater than the calculated time, the internal oscillator block is running too fast; to compensate, decrement the OSCTUNE register. If the measured time is less than the calculated time, the inter- nal oscillator block is running too slow; to compensate, increment the OSCTUNE register. |
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