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PIC18LF26J53 Datasheet(PDF) 35 Page - Microchip Technology

Part No. PIC18LF26J53
Description  28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology
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Maker  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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PIC18LF26J53 Datasheet(HTML) 35 Page - Microchip Technology

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 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 35
PIC18F47J53 FAMILY
3.0
OSCILLATOR
CONFIGURATIONS
3.1
Overview
Devices in the PIC18F47J53 family incorporate a
different oscillator and microcontroller clock system
than general purpose PIC18F devices. Besides the
USB module, with its unique requirements for a stable
clock source, make it is necessary to provide a
separate clock source that is compliant with both USB
low-speed and full-speed specifications.
The PIC18F47J53 family has additional prescalers and
postscalers, which have been added to accommodate
a wide range of oscillator frequencies. Figure 3-1
provides an overview of the oscillator structure.
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.
3.1.1
OSCILLATOR CONTROL
The operation of the oscillator in PIC18F47J53 family
devices is controlled through three Configuration regis-
ters and two control registers. Configuration registers,
CONFIG1L, CONFIG1H and CONFIG2L, select the
oscillator mode, PLL prescaler and CPU divider
options. As Configuration bits, these are set when the
device is programmed and left in that configuration until
the device is reprogrammed.
The OSCCON register (Register 3-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 3.5.1 “Oscillator Control
Register”.
The OSCTUNE register (Register 3-1) is used to trim the
INTOSC frequency source and select the low-frequency
clock source that drives several special features. The
OSCTUNE register is also used to activate or disable the
Phase Locked Loop (PLL). Its use is described in
Section 3.2.5.1 “OSCTUNE Register”.
3.2
Oscillator Types
PIC18F47J53 family devices can be operated in eight
distinct oscillator modes. Users can program the
FOSC<2:0> Configuration bits to select one of the
modes listed in Table 3-1. For oscillator modes which
produce a clock output (CLKO) on pin RA6, the output
frequency will be one fourth of the peripheral clock
frequency. The clock output stops when in Sleep mode,
but will continue during Idle mode (see Figure 3-1).
3.2.1
OSCILLATOR MODES AND
USB OPERATION
Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In
order to use the USB module, a fixed 6 MHz or 48 MHz
clock must be internally provided to the USB module for
operation in either Low-Speed or Full-Speed mode,
respectively. The microcontroller core need not be
clocked at the same frequency as the USB module.
A network of MUXes, clock dividers and a fixed 96 MHz
output PLL have been provided, which can be used to
derive various microcontroller core and USB module
frequencies. Figure 3-1 helps in understanding the
oscillator structure of the PIC18F47J53 family of
devices.
TABLE 3-1:
OSCILLATOR MODES
Mode
Description
ECPLL
External Clock Input mode, the PLL can
be enabled or disabled in software,
CLKO on RA6, apply external clock
signal to RA7.
EC
External Clock Input mode, the PLL is
always disabled, CLKO on RA6, apply
external clock signal to RA7.
HSPLL
High-Speed Crystal/Resonator mode,
PLL can be enabled or disabled in
software, crystal/resonator connected
between RA6 and RA7.
HS
High-Speed Crystal/Resonator mode,
PLL always disabled, crystal/resonator
connected between RA6 and RA7.
INTOSCPLLO Internal Oscillator mode, PLL can be
enabled or disabled in software, CLKO
on RA6, port function on RA7, the
internal oscillator block is used to derive
both the primary clock source and the
postscaled internal clock.
INTOSCPLL Internal Oscillator mode, PLL can be
enabled or disabled in software, port
function on RA6 and RA7, the internal
oscillator block is used to derive both the
primary clock source and the postscaled
internal clock.
INTOSCO
Internal Oscillator mode, PLL is always
disabled, CLKO on RA6, port function on
RA7, the output of the INTOSC
postscaler serves as both the postscaled
internal clock and the primary clock
source.
INTOSC
Internal Oscillator mode, PLL is always
disabled, port function on RA6 and RA7,
the output of the INTOSC postscaler
serves as both the postscaled internal
clock and the primary clock source.


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