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HT82M75REW Datasheet(PDF) 61 Page - Holtek Semiconductor Inc |
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HT82M75REW Datasheet(HTML) 61 Page - Holtek Semiconductor Inc |
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61 / 103 page  HT82M75REW/HT82K75REW Rev. 1.00 61 June 11, 2010 Typical RF Transceiver TX Operation The TXMAC inside the RF Transceiver will automatically generate the preamble, Start-of-Frame Delimiter and the FCS when transmitting. The MCU host must write all other frame fields into TXFIFO for TX operation. To send a packet in TX FIFO, there are several steps to follow: Fill necessary data in TXFIFO. The format of TXFIFO is as follows: ¨ TXFIFO Address 0x001 0x0+N 1 Byte 4 Bytes 1 Byte N Bytes Frame Length Destination Address Frame Control Payload · Set Ackreq by SREG0x1B [2], if an acknowledgement / retransmission is required. The RF Transceiver automatically retransmits the packet till the number of the Max trial times specified in SREG1B [7:4] is reached, if there is no ac- knowledgement received. · By triggering SREG0x1B [0], the TXMAC will send the packet immediately. This bit will be automatically cleared. · Wait for the interrupt status shown in SREG0x31 [0]. If retransmission is not required, SREG0x31 [0] indicates the packet is successfully transmitted. · Check SREG0x24 [0] to see if transmission is successful. If SREG0x24 [0] is equal to 0, it means that the transmis- sion is successful and the ACK was received. The number of times of the retransmission can be read at SREG0x24 [7:4]. If SREG0x24 [0] is equal to 1, it means that the transmission failed and ACK was not received. Registers associated with Typical TX Operation Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR 0x1B TXTRIG TXRTYN3 TXRTYN2 TXRTYN1 TXRTYN0 r TXACKREQ r TXTRIG 0011 0000 0x24 TXSR TXRETRY3 TXRETRY2 TXRETRY1 TXRETRY0 r r r TXNS 0000 0000 0x31 ISRSTS r WAKEIF r r RXIF r r TXNIF 0000 0000 Typical RF Transceiver RX Operation When a valid packet is received, an interrupt is issued at SREG0x31 [3]. The MCU host can read the whole packet in- side the RXFIFO. The RXFIFO is flushed when the frame length field and the last byte of RXFIFO are read, or when the MCU host triggers a RX flush by SREG0x0D [0]. The format of RXFIFO is as follows: · RXFIFO Address 0x300 0x307+N 1 Byte 4 Bytes 1 Byte N Byte 1 Bytes Frame Length Destination Address Frame Control Payload Frame Control · Registers associated with Typical RX Operation Addr. File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR 0x0D RXFLUSH rrrrr PTX r RXFLUSH 0110 0000 0x31 ISRSTS r WAKEIF r r RXIF r r TXNIF 0000 0000 |
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