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IDT82V3385 Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT82V3385 Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 145 page  9 May 14, 2010 IDT82V3385 2010 Integrated Device Technology, Inc. DSC-7211/5 SYNCHRONOUS ETHERNET WAN PLL IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. FEATURES HIGHLIGHTS • The first single PLL chip: • Features 0.5 mHz to 560 Hz bandwidth • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements • Provides node clocks for Cellular and WLL base-station (GSM and 3G networks) • Provides clocks for DSL access concentrators (DSLAM), espe- cially for Japan TCM-ISDN network timing based ADSL equip- ments MAIN FEATURES • Provides an integrated single-chip solution for Synchronous Equip- ment Timing Source, including Stratum 2, 3E, 3, SMC, 4E and 4 clocks • Employs DPLL and APLL to feature excellent jitter performance and minimize the number of the external components • Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or locks to T0 DPLL • Supports Forced or Automatic operating mode switch controlled by an internal state machine; the primary operating modes are Free- Run, Locked and Holdover • Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19 steps) and damping factor (1.2 to 20 in 5 steps) • Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy • Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61 ns • Supports phase absorption when phase-time changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds • Supports programmable input-to-output phase offset adjustment • Limits the phase and frequency offset of the outputs • Supports manual and automatic selected input clock switch • Supports automatic hitless selected input clock switch on clock fail- ure • Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing • Provides a 2 kHz, 4 kHz or 8 kHz frame sync input signal, and a 2 kHz and an 8 kHz frame sync output signals • Provides 5 input clocks whose frequency cover from 2 kHz to 622.08 MHz • Provides 5 output clocks whose frequency cover from 1 Hz to 622.08 MHz • Provides output clocks for BITS, GPS, 3G, GSM, etc. • Supports PECL/LVDS and CMOS input/output technologies • Supports master clock calibration • Supports Master/Slave application (two chips used together) to enable system protection against single chip failure • Meets Telcordia GR-1244-CORE, GR-253-CORE, GR-1377- CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria OTHER FEATURES • Multiple microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola and Serial • IEEE 1149.1 JTAG Boundary Scan • Single 3.3 V operation with 5 V tolerant CMOS I/Os • 100-pin TQFP package, Green package options available APPLICATIONS • BITS / SSU • SMC / SEC (SONET / SDH) • DWDM cross-connect and transmission equipments • Synchronous Ethernet equipments • Central Office Timing Source and Distribution • Core and access IP switches / routers • Gigabit and Terabit IP switches / routers • IP and ATM core switches and access equipments • Cellular and WLL base-station node clocks • Broadband and multi-service access equipments • Any other telecom equipments that need synchronous equipment system timing |
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