CDCM61004

www.ti.com

SCAS871D – FEBRUARY 2009 – REVISED FEBRUARY 2010

Four Output, Integrated VCO, Low-Jitter Clock Generator

Check for Samples: CDCM61004

1

FEATURES

•

Low Output Skew of 30 ps on LVPECL Outputs

2

•

One Crystal Reference Input Including 24.8832

•

Divider Programming Using Control Pins:

MHz, 25 MHz, and 26.5625 MHz

–

Two Pins for Prescaler/Feedback Divider

•

Input Frequency Range: 21.875 MHz to

–

Three Pins for Output Divider

28.47 MHz

–

Two Pins for Output Select

•

On-Chip VCO Operates in Frequency Range of

•

Chip Enable Control Pin Available

1.75 GHz to 2.05 GHz

•

3.3-V Core and I/O Power Supply

•

4x Output Available:

•

Industrial Temperature Range: –40°C to +85°C

–

Pin-Selectable Between LVPECL, LVDS, or

•

5-mm × 5-mm, 32-pin, QFN (RHB) Package

2-LVCMOS; Operates at 3.3 V

•

ESD Protection Exceeds 2 kV (HBM)

•

LVCMOS Bypass Output Available

•

Output Frequency Selectable by /1, /2, /3, /4, /6,

APPLICATIONS

/8 from a Single Output Divider

•

Low Jitter Clock Driver for High-End Datacom

•

Supports Common LVPECL/LVDS Output

Applications Including SONET, Ethernet, Fibre

Frequencies:

Channel, Serial ATA, and HDTV

–

62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,

•

Cost-Effective High-Frequency Crystal

Oscillator Replacement

100 MHz, 106.25 MHz, 125 MHz, 150 MHz,

155.52 MHz, 156.25 MHz, 159.375 MHz,

187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz,

311.04 MHz, 312.5 MHz, 622.08 MHz,

DESCRIPTION

625 MHz

The CDCM61004 is a highly versatile, low-jitter

•

Supports Common LVCMOS Output

frequency synthesizer that can generate four low-jitter

Frequencies:

clock

outputs,

selectable

between

low-voltage

positive emitter coupled logic (LVPECL), low-voltage

–

62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,

differential

signaling

(LVDS),

or

low-voltage

100 MHz, 106.25 MHz, 125 MHz, 150 MHz,

complementary

metal

oxide

semiconductor

155.52 MHz, 156.25 MHz, 159.375 MHz,

(LVCMOS) outputs, from a low-frequency crystal for a

187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz

variety

of

wireline

and

data

communication

•

Output Frequency Range: 43.75 MHz to

applications. The CDCM61004 features an onboard

683.264 MHz (See Table 3)

PLL that can be easily configured solely through

control

pins.

The

overall

output

random

jitter

•

Internal PLL Loop Bandwidth: 400 kHz

performance is less than 1ps, RMS (from 10 kHz to

•

High-Performance PLL Core:

20 MHz), making this device a perfect choice for use

–

Phase Noise typically at –146 dBc/Hz at

in demanding applications such as SONET, Ethernet,

5-MHz Offset for 625-MHz LVPECL Output

Fibre Channel, and SAN. The CDCM61004 is

available in a small, 32-pin,

5-mm × 5-mm QFN

–

Random Jitter typically at 0.509 ps, RMS

package.

(10 kHz to 20 MHz) for 625-MHz LVPECL

Output

•

Output Duty Cycle Corrected to 50% (± 5%)

1

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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

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PRODUCTION DATA information is current as of publication date.

Copyright © 2009–2010, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.