Technical Note

27/40

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2009.09 - Rev.D

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BR24L□□-W Series,BR24S□□□-W Series

Vcc

SCL

GND

BR24S08-W

BR24S16-W

BR24S32-W

BR24S64-W

BR24S128-W

BR24S256-W

1

2

3

4

5

6

7

8

WP

SDA

A2

A1

A0

●

I

○

I

I

and acknowledge is always required after each byte.

I

serial clock (SCL).

Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is

controlled by addresses peculiar to devices.

EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,

and the device that receives data is called “receiver”.

○

Start condition (start bit recognition)

・

Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH'

is necessary.

・

This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is

satisfied, any command is executed.

○

Stop condition (stop bit recognition)

・

Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'

○

Acknowledge (ACK) signal

・

This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master

and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data output of read

command) at the transmitter (sending) side releases the bus after output of 8bit data.

・

The device (this IC at slave address input of write command, read command, and μ-COM at data output of read

command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK

signal) showing that it has received the 8bit data.

・

This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.

・

Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).

・

Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.

・

When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this IC

continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes

stop condition (stop bit), and ends read action. And this IC gets in standby status.

○

Device addressing

・

Output slave address after start condition from master.

・

The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.

・

Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus

according to the number of device addresses.

・

The most insignificant bit (R/W --- READ/WRITE) of slave address is used for designating write or read action, and is as

shown below.

Setting R/W to 0 --- write (setting 0 to word address setting of random read)

Setting R/W to 1 --- read

P0～P2 are page select bits.

Note) Up to 2 units of BR24S08-W, up to 1 units of BR24S16-W, and up to 8 units of BR24S32/64/128/256-W can be connected.

Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.

Type

Slave address

Maximum number of

connected buses

BR24S08-W

1 0 1 0 A2 P1 P0 R/W

―

2

BR24S16-W

1 0 1 0 P2 P1 P0 R/W

―

1

BR24S32-W, BR24S64-W

BR24S128-W, BR24S256-W

1 0 1 0 A2 A1 A0 R/W

―

8

89

89

89

S

P

condition

condition

ACK

STOP

ACK

DATA

DATA

ADDRESS

START

R/W

ACK

1-7

SDA

SCL

1-7

1-7

Fig.32 Data transfer timing