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STM660OAS54DM6F Datasheet(PDF) 8 Page - STMicroelectronics |
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STM660OAS54DM6F Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 51 page Description STM6600 - STM6601 8/51 Doc ID 15453 Rev 7 Figure 6. Block diagram 1. Internal pull-up resistor connected to PB input (see Table 5 for precise specifications). 2. Optional internal pull-up resistor connected to SR input (see Table 5 for precise specifications and Table 10 for detailed device options). 3. Internal pull-down resistor is connected to PSHOLD input only during startup (see Figure 7, 8, 9, 10, 11, 12, 13, and 18). VTH+ PB EN (EN) Smart logic Edge detector debounce SRD logic GND CSRD tREC generator INT RST PS HOLD VCC VCCLO VREF Glitch immunity PBOUT AM00237v3 1.5 V Edge detector debounce Glitch immunity + – VTH– + – SR R PSHOLD (3) V CC V CC R PB R SR (1) (2) |
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