SC68C652BIB48 datasheet(10/43 Pages) NXP

Part #	SC68C652BIB48

Description	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and 68 mode mP interface

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Manufacturer	NXP [NXP Semiconductors]

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10 / 43 page

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

10 of 43

NXP Semiconductors

SC68C652B

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

6.4 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC68C652B monitors the CTSn pin

for a remote buffer overﬂow indication and controls the RTSn pin for local buffer overﬂows.

Automatic hardware ﬂow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to

a logic 1. If CTSn transitions from a logic 0 to a logic 1 indicating a ﬂow control request,

ISR[5] will be set to a logic 1 (if enabled via IER[6:7]), and the SC68C652B will suspend

TXn transmissions as soon as the stop bit of the character in process is shifted out.

Transmission is resumed after the CTSn input returns to a logic 0, indicating more data

may be sent.

With the auto-RTS function enabled, an interrupt is generated when the receive FIFO

reaches the programmed trigger level. The RTSn pin will not be forced to a logic 1 (RTS

off), until the receive FIFO reaches the next trigger level. However, the RTSn pin will return

to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the

programmed trigger level. However, under the above described conditions, the

SC68C652B will continue to accept data until the receive FIFO is full.

6.5 Software ﬂow control

When software ﬂow control is enabled, the SC68C652B compares one or two sequential

receive data characters with the programmed Xon or Xoff character value(s). If received

character(s) match the programmed Xoff values, the SC68C652B will halt transmission

as soon as the current character(s) has completed transmission. When a match occurs,

the receive ready (if enabled via Xoff IER[5]) ﬂags will be set and the interrupt output pin

(if receive interrupt is enabled) will be activated. Following a suspension due to a match of

the Xoff characters’ values, the SC68C652B will monitor the receive data stream for a

match to the Xon1/Xon2 character value(s). If a match is found, the SC68C652B will

resume operation and clear the ﬂags (ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow control.

Different conditions can be set to detect Xon/Xoff characters and suspend/resume

transmissions. When double 8-bit Xon/Xoff characters are selected, the SC68C652B

compares two consecutive receive characters with two software ﬂow control 8-bit values

(Xon1, Xon2, Xoff1, Xoff2) and controls TXn transmissions accordingly. Under the above

described ﬂow control mechanisms, ﬂow control characters are not placed (stacked) in the

user accessible receive data buffer or FIFO. When using a software ﬂow control, the

Xon/Xoff characters cannot be used for data transfer.

In the event that the receive buffer is overﬁlling and ﬂow control needs to be executed, the

SC68C652B automatically sends an Xoff message (when enabled) via the serial TXn

output to the remote modem. The SC68C652B sends the Xoff1/Xoff2 characters as soon

Table 5.

Flow control mechanism

Selected trigger level

(characters)

IRQ pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

RX

TX

88

16

8

0

16

8

16

7

24

15

28

30

28

23

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