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SC28L92A1A Datasheet(PDF) 30 Page - NXP Semiconductors |
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SC28L92A1A Datasheet(HTML) 30 Page - NXP Semiconductors |
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30 / 73 page  SC28L92_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 19 December 2007 30 of 73 NXP Semiconductors SC28L92 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 5 - Channel A transmitter Request To Send (RTS) control. 0 = No RTS control 1 = RTS control This bit controls the deactivation of the RTSAN output (OP0) by the transmitter. This output is normally asserted by setting OPR[0] and negated by resetting OPR[0]. MR2A[5] = 1 caused OPR[0] to be reset automatically one bit time after the characters in the channel A transmit shift register and in the Tx FIFO, if any, are completely transmitted including the programmed number of stop bits, if the transmitter is not enabled This feature can be used to automatically terminate the transmission of a message as follows (line turnaround): 1. Program auto-reset mode: MR2A[5] = 1 2. Enable transmitter 3. Assert RTSAN: OPR[0] = 1 4. Send message 5. Disable transmitter after the last character is loaded into the channel A Tx FIFO 6. The last character will be transmitted and OPR[0] will be reset one bit time after the last stop bit, causing RTSAN to be negated 4 - Channel A transmitter Clear To Send (CTS) control. 0 = Input CTSAN(IP0) has no effect on the transmitter 1 = CTS control enabled If this bit is a 1, the transmitter checks the state of CTSAN (IP0) each time it is ready to send a character. If IP0 is asserted (LOW), the character is transmitted. If it is negated (HIGH), the TxDA output remains in the marking state and the transmission is delayed until CTSAN goes LOW. Changes in CTSAN while a character is being transmitted do not affect the transmission of that character. 3 to 0 - Stop bit length select. This field programs the length of the stop bit appended to the transmitted character. Stop bit lengths of 9 ⁄16 to 1 and 1 − 9⁄ 16 to 2 bits, in increments of 1 ⁄16 bit, can be programmed for character lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1 − 1⁄ 16 to 2 stop bits can be programmed in increments of 1 ⁄16 bit. In all cases, the receiver only checks for a mark condition at the center of the stop bit position (one half-bit time after the last data bit, or after the parity bit if enabled is sampled). Refer to Table 32 for the values. If an external 1 × clock is used for the transmitter: MR2A[3] = 0 selects one stop bit MR2A[3] = 1 selects two stop bits Table 30. MR2A - Mode Register 2 channel A (address 0x0) bit description …continued Bit Symbol Description |
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