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SC28L92 Datasheet(PDF) 45 Page - NXP Semiconductors |
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SC28L92 Datasheet(HTML) 45 Page - NXP Semiconductors |
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45 / 73 page  SC28L92_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 19 December 2007 45 of 73 NXP Semiconductors SC28L92 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.10 Input Port Change Register (IPCR) 7.3.11 Interrupt Status Register (ISR) This register provides the status of all potential interrupt sources. The contents of this register are masked by the Interrupt Mask Register (IMR). If a bit in the ISR is a logic 1 and the corresponding bit in the IMR is also a logic 1, the INTRN output will be asserted (LOW). If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR. The true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to 0x0 when the DUART is reset. Table 55. IPCR - Input port change register (address 0x4) bit allocation 7 6 5 4 3 2 1 0 delta IP3 delta IP2 delta IP1 delta IP0 state of IP3 state of IP2 state of IP1 state of IP0 Table 56. IPCR - Input port change register (address 0x4) bit description Bit Symbol Description 7 to 4 - IP3, IP2, IP1 and IP0 change of state. 0 = no change 1 = change These bits are set when a change of state, as defined in Section 6.2.9 “Input port”, occurs at the respective input pins. They are cleared when the IPCR is read by the CPU. A read of the IPCR also clears ISR[7], the input change bit in the interrupt status register. The setting of these bits can be programmed to generate an interrupt to the CPU. 3 to 0 - IP3, IP2, IP1 and IP0 state. 0 = LOW 1 = HIGH These bits provide the current state of the respective inputs. The information is unlatched and reflects the state of the input pins at the time the IPCR is read. Table 57. ISR - Interrupt status register (address 0x5) bit allocation 7 6 5 4 3 2 1 0 change input port change break B RxRDYB TxRDYB counter ready change break A RxRDYA TxRDYA Table 58. ISR - Interrupt status register (address 0x5) bit description Bit Symbol Description 7 - Input port change status. 0 = not active 1 = active This bit is a logic 1 when a change of state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event has been selected to cause an interrupt by the programming of ACR[3:0]. The bit is cleared when the CPU reads the IPCR. |
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