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SC16IS752 Datasheet(PDF) 44 Page - NXP Semiconductors |
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SC16IS752 Datasheet(HTML) 44 Page - NXP Semiconductors |
44 / 59 page ![]() SC16IS752_SC16IS762_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 19 May 2008 44 of 59 NXP Semiconductors SC16IS752/SC16IS762 Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR [1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage tolerance on inputs and outputs when no supply voltage is present. [2] XTAL2 should be left open when XTAL1 is driven by an external clock. I2C-bus inputs SCL, CS/A0, SI/A1 VIH HIGH-level input voltage 1.6 5.5[1] 2.0 5.5[1] V VIL LOW-level input voltage - 0.6 - 0.8 V IL leakage current input; VI = 0 V or 5.5 V[1] -10-10 µA Ci input capacitance -7-7 pF Clock input XTAL1[2] VIH HIGH-level input voltage 1.8 5.5[1] 2.4 5.5[1] V VIL LOW-level input voltage - 0.45 - 0.6 V IL leakage current input; VI = 0 V or 5.5 V[1] −30 +30 −30 +30 µA Ci input capacitance -3-3 pF Sleep current IDD(sleep) sleep mode supply current inputs are at VDD or ground - 30 - 30 µA Table 36. Static characteristics …continued VDD = 2.5 V ± 0.2 V, Tamb = −40 °Cto+85 °C; or VDD = 3.3 V ± 0.3 V, Tamb = −40 °Cto+95 °C; unless otherwise specified. Symbol Parameter Conditions VDD = 2.5 V VDD = 3.3 V Unit Min Max Min Max |
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