Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

SC16IS752 Datasheet(PDF) 31 Page - NXP Semiconductors

Part No. SC16IS752
Description  Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
Download  59 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC16IS752 Datasheet(HTML) 31 Page - NXP Semiconductors

Back Button SC16IS752 Datasheet HTML 27Page - NXP Semiconductors SC16IS752 Datasheet HTML 28Page - NXP Semiconductors SC16IS752 Datasheet HTML 29Page - NXP Semiconductors SC16IS752 Datasheet HTML 30Page - NXP Semiconductors SC16IS752 Datasheet HTML 31Page - NXP Semiconductors SC16IS752 Datasheet HTML 32Page - NXP Semiconductors SC16IS752 Datasheet HTML 33Page - NXP Semiconductors SC16IS752 Datasheet HTML 34Page - NXP Semiconductors SC16IS752 Datasheet HTML 35Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 31 / 59 page
background image
SC16IS752_SC16IS762_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 19 May 2008
31 of 59
NXP Semiconductors
SC16IS752/SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.17 I/O Interrupt Enable register (IOIntEna)
This register enables the interrupt due to a change in the I/O configured as inputs. If
GPIO[7:4] or GPIO[3:0] are programmed as modem pins, their interrupt generation must
be enabled via IER[3]. In this case, IOIntEna will have no effect on GPIO[7:4] or
GPIO[3:0].
8.18 I/O Control register (IOControl)
Remark: As I/O pins, the direction, state, and interrupt enable of GPIO are controlled by
the following registers: IODir, IOState, IOIntEna, and IOControl. The state of CD, RI, DSR
pins will not be reflected in MSR[7:5] or MSR[3:1], and any change of state on these three
pins will not trigger a modem status interrupt (even if enabled via IER[3]), and the state of
the DTR pin cannot be controlled by MCR[0].
As modem CD, RI, DSR pins, the status at the input of these three pins can be read from
MSR[7:5] and MSR[3:1], and the state of the DTR pin can be controlled by MCR[0]. Also,
if modem status interrupt bit is enabled, IER[3], a change of state on RI, CD, DSR pins will
trigger a modem interrupt. The IODir, IOState, and IOIntEna registers will not have any
effect on these three pins.
Table 28.
IOIntEna register bits description
Bit
Symbol
Description
7:0
IOIntEna
Input interrupt enable.
0 = a change in the input pin will not generate an interrupt
1 = a change in the input will generate an interrupt
Table 29.
IOControl register bits description
Bit
Symbol
Description
7:4
reserved
These bits are reserved for future use.
3
SRESET
Software Reset. A write to this bit will reset the device. Once the
device is reset this bit is automatically set to logic 0.
2
GPIO[3:0] or
RIB, CDB,
DTRB, DSRB
This bit programs GPIO[3:0] as I/O pins or as modem pins.
0 = I/O pins
1 = GPIO[3:0] emulate RIB, CDB, DTRB, DSRB
1
GPIO[7:4] or
RIA, CDA,
DTRA, DSRA
This bit programs GPIO[7:4] as I/O pins or as modem pins.
0 = I/O pins
1 = GPIO[7:4] emulate RIA, CDA, DTRA, DSRA
0
IOLATCH
Enable/disable inputs latching.
0 = input value are not latched. A change in any input generates an
interrupt. A read of the input register clears the interrupt. If the input
goes back to its initial logic state before the input register is read,
then the interrupt is cleared.
1 = input values are latched. A change in the input generates an
interrupt and the input logic value is loaded in the bit of the
corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial
logic state before the interrupt register is read, then the interrupt is
not cleared and the corresponding bit of the IOState register keeps
the logic value that initiates the interrupt.


Similar Part No. - SC16IS752

ManufacturerPart No.DatasheetDescription
NXP Semiconductors
NXP Semiconductors
SC16IS752 NXP-SC16IS752 Datasheet
727Kb / 8P
   Smart, simple solutions for the 12 most common design concerns
August 2011
SC16IS752 NXP-SC16IS752 Datasheet
482Kb / 60P
   Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
Rev. 9-22 March 2012
SC16IS752IBS NXP-SC16IS752IBS Datasheet
482Kb / 60P
   Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
Rev. 9-22 March 2012
More results

Similar Description - SC16IS752

ManufacturerPart No.DatasheetDescription
NXP Semiconductors
NXP Semiconductors
SC16IS752IBS NXP-SC16IS752IBS Datasheet
482Kb / 60P
   Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
Rev. 9-22 March 2012
SC16IS740 NXP-SC16IS740 Datasheet
321Kb / 62P
   Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
Rev. 06-13 May 2008
SC16IS740 PHILIPS-SC16IS740 Datasheet
308Kb / 62P
   Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
Rev. 05-16 November 2006
SC16IS740 NXP-SC16IS740_11 Datasheet
555Kb / 63P
   Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs
Rev. 7-9 June 2011
SC16C652 PHILIPS-SC16C652 Datasheet
575Kb / 41P
   Dual UART with 32 bytes of transmit and receive FIFOs
Rev. 04-20 June 2003
SC16C2550 PHILIPS-SC16C2550 Datasheet
603Kb / 46P
   Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
Rev. 03-19 June 2003
SC16C2550 PHILIPS-SC16C2550 Datasheet
603Kb / 46P
   Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
Rev. 03-19 June 2003
Exar Corporation
Exar Corporation
ST16C2550 EXAR-ST16C2550 Datasheet
443Kb / 34P
   DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFOS
NXP Semiconductors
NXP Semiconductors
SC16C2552 PHILIPS-SC16C2552 Datasheet
579Kb / 38P
   Dual UART with 16-byte transmit and receive FIFOs
Rev. 03-20 June 2003
SC16C852V NXP-SC16C852V Datasheet
253Kb / 54P
   Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Rev. 03-15 October 2007
More results


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz