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SC16IS752 Datasheet(PDF) 30 Page - NXP Semiconductors

Part No. SC16IS752
Description  Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC16IS752 Datasheet(HTML) 30 Page - NXP Semiconductors

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SC16IS752_SC16IS762_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 19 May 2008
30 of 59
NXP Semiconductors
SC16IS752/SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.13 Transmitter FIFO Level register (TXLVL)
This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.
8.14 Receiver FIFO Level register (RXLVL)
This register is a read-only register, it reports the fill level of the receive FIFO, that is, the
number of characters in the RX FIFO.
8.15 Programmable I/O pins Direction register (IODir)
This register is used to program the I/O pins direction. Bit 0 to bit 7 controls GPIO0 to
GPIO7.
8.16 Programmable I/O pins State register (IOState)
When ‘read’, this register returns the actual state of all I/O pins. When ‘write’, each
register bit will be transferred to the corresponding I/O pin programmed as output.
Table 24.
Transmitter FIFO Level register bits description
Bit
Symbol
Description
7
-
not used; set to zeros
6:0
TXLVL[6:0]
number of spaces available in TX FIFO, from 0 (0x00) to 64 (0x40)
Table 25.
Receiver FIFO Level register bits description
Bit
Symbol
Description
7
-
not used; set to zeros
6:0
RXLVL[6:0]
number of characters stored in RX FIFO, from 0 (0x00) to 64 (0x40)
Table 26.
IODir register bits description
Bit
Symbol
Description
7:0
IODir
Set GPIO pins [7:0] to input or output.
0 = input
1 = output
Table 27.
IOState register bits description
Bit
Symbol
Description
7:0
IOState
Write this register: set the logic level on the output pins
0 = set output pin to zero
1 = set output pin to one
Read this register: return states of all pins


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