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SC16IS752 Datasheet(PDF) 23 Page - NXP Semiconductors

Part No. SC16IS752
Description  Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC16IS752 Datasheet(HTML) 23 Page - NXP Semiconductors

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SC16IS752_SC16IS762_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 19 May 2008
23 of 59
NXP Semiconductors
SC16IS752/SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1]
IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will not
cause a new interrupt if the THR is below the threshold.
8.4 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels. Table 12 shows FIFO Control Register bit settings.
[1]
FIFO reset logic requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of
the XTAL1 clock.
1
IER[1]
Transmit Holding Register interrupt.
logic 0 = disable the THR interrupt (normal default condition)
logic 1 = enable the THR interrupt
0
IER[0]
Receive Holding Register interrupt.
logic 0 = disable the RHR interrupt (normal default condition)
logic 1 = enable the RHR interrupt
Table 11.
Interrupt Enable Register bits description …continued
Bit
Symbol
Description
Table 12.
FIFO Control Register bits description
Bit
Symbol
Description
7:6
FCR[7] (MSB),
FCR[6] (LSB)
RX trigger. Sets the trigger level for the RX FIFO.
00 = 8 characters
01 = 16 characters
10 = 56 characters
11 = 60 characters
5:4
FCR[5] (MSB),
FCR[4] (LSB)
TX trigger. Sets the trigger level for the TX FIFO.
00 = 8 spaces
01 = 16 spaces
10 = 32 spaces
11 = 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
3
FCR[3]
reserved
2
FCR[2][1]
Reset TX FIFO.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
level logic (the Transmit Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
1
FCR[1][1]
Reset RX FIFO
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
level logic (the Receive Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO


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