PTN3300A_1

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 01 — 30 June 2008

2 of 23

NXP Semiconductors

PTN3300A

DVI/HDMI level shifter with inverting 1.1 V HPD

Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].

Fig 1.

Typical application system diagram

002aad645

OUT_D1

−

OUT_D1+

IN_D1

−

IN_D1+

HPD_SOURCE_N

HPD_SINK

SCL_SINK

SDA_SINK

DDC_EN

(0 V to 3.3 V)

SCL_SOURCE

SDA_SOURCE

OUT_D2

−

OUT_D2+

IN_D2

−

IN_D2+

OUT_D3

−

OUT_D3+

IN_D3

−

IN_D3+

OUT_D4

−

OUT_D4+

IN_D4

−

IN_D4+

PTN3300A

OE_N

5 V

5 V

0 V to 5 V

0 V to 1.1 V

3.3 V

3.3 V

3.3 V

AC-coupled

differential pair

clock

CLOCK LANE

DATA LANE

DATA LANE

DATA LANE

AC-coupled

differential pair

TMDS data

AC-coupled

differential pair

TMDS data

AC-coupled

differential pair

TMDS data

TX

TX

FF

TMDS

clock

pattern

MULTI-MODE DISPLAY SOURCE

TX

TX

FF

TMDS

coded

data

TX

TX

FF

TMDS

coded

data

TX

TX

FF

TMDS

coded

data

PCIe PHY ELECTRICAL

CONFIGURATION

DDC I/O

PCIe

output buffer

reconfigurable I/Os

PCIe

output buffer

PCIe

output buffer

PCIe

output buffer