PRTR5V0U8S_1

© NXP B.V. 2008. All rights reserved.

Preliminary data sheet

Rev. 01 — 14 January 2008

2 of 7

NXP Semiconductors

PRTR5V0U8S

Integrated octal low-capacity ESD protection

2.

Pinning information

3.

Ordering information

4.

Limiting values

Table 1.

Pinning

Pin

Description

Simplified outline

Symbol

1

ESD protection I/O 1

2

ESD protection I/O 2

3

ground (GND)

4

ESD protection I/O 3

5

ESD protection I/O 4

6

ESD protection I/O 5

7

ESD protection I/O 6

8

9

ESD protection I/O 7

10

ESD protection I/O 8

15

10

6

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1

2

3

4

5

10

9

8

7

6

Table 2.

Ordering information

Type number

Package

Name

Description

Version

PRTR5V0U8S

TSSOP10

plastic thin shrink small outline package; 10 leads;

body width 3 mm

SOT552-1

Table 3.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

input/output to ground voltage

0

5.5

V

storage temperature

−55

+125

°C

Table 4.

ESD standards compliance

Standard

Conditions

Per diode

IEC 61000-4-2; level 4 (ESD)

≤ 8 kV (contact)