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591MC148M352DGR Datasheet(PDF) 1 Page - Silicon Laboratories

Part # 591MC148M352DGR
Description  1 ps MAX JITTER CRYSTAL OSCILLATOR
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

591MC148M352DGR Datasheet(HTML) 1 Page - Silicon Laboratories

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Preliminary Rev. 0.25 7/09
Copyright © 2009 by Silicon Laboratories
Si590/591
Si590/591
1 ps M AX J ITTER C RYSTAL O SCILLATOR (XO)
(10 M H Z TO 525 MH Z)
Features
Applications
Description
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry
to provide a low jitter clock at high frequencies. The Si590/591 is available
with any-rate output frequency from 10 to 525 MHz. Unlike a traditional XO,
where a unique crystal is required for each output frequency, the Si590/591
uses one fixed crystal to provide a wide range of output frequencies. This IC
based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis provides
superior supply noise rejection, simplifying the task of generating low jitter
clocks in noisy environments typically found in communication systems. The
Si590/591 IC based XO is factory configurable for a wide variety of user
specifications including frequency, supply voltage, output format, and
temperature stability. Specific configurations are factory programmed at time
of shipment, thereby eliminating long lead times associated with custom
oscillators.
Functional Block Diagram
Available with any-rate output
frequencies from 10 MHz to 525 MHz
3rd generation DSPLL® with superior
jitter performance: 1 ps max jitter
Better frequency stability than SAW-
based oscillators
Internal fundamental mode crystal
ensures high reliability
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating
temperature range
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
Test and measurement
Storage
FPGA/ASIC clock generation
Fixed
Frequency
XO
Any-rate
10–525 MHz
DSPLL
®
Clock
Synthesis
VDD
CLK+
CLK–
GND
OE
17 k *
17 k *
*Note: Output Enable High/Low Options Available – See Ordering Information
Ordering Information:
See page 6.
Pin Assignments:
See page 5.
(Top View)
Si5602
1
2
3
6
5
4
GND
OE
VDD
CLK+
CLK–
NC
1
2
3
6
5
4
GND
NC
VDD
CLK
NC
OE
1
2
3
6
5
4
GND
NC
VDD
CLK+
CLK–
OE
Si590 (LVDS/LVPECL/CML)
Si590 (CMOS)
Si591 (LVDS/LVPECL/CML)


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