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DAC8728SPAG Datasheet(PDF) 10 Page - Texas Instruments |
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DAC8728SPAG Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 52 page  48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 D2 D1 D0 NC V -4 REF-B V -5 AV AGND-B V -6 AV OFFSET-B V -7 NC RSTSEL GPIO OUT OUT DD OUT SS OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D13 D14 D15 V V -3 REF-A V -2 AV AGND-A V -1 AV OFFSET-A V -0 NC /BTC USB BUSY MON OUT OUT DD OUT SS OUT DAC8728 D13 D14 D15 V V -3 REF-A V -2 AV AGND-A V -1 AV OFFSET-A V -0 /BTC USB MON OUT OUT DD OUT SS OUT D3 D2 D1 D0 NC V -4 REF-B V -5 AV AGND-B V -6 AV OFFSET-B V -7 OUT DD SS OUT OUT OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 DAC8728 DAC8728 SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009 www.ti.com PIN CONFIGURATIONS PAG PACKAGE RTQ PACKAGE TQFP-64 QFN-56 (TOP VIEW) (TOP VIEW) (1) The thermal pad is internally connected to the substrate. This pad can be connected to AVSS or left floating. Keep the thermal pad separate from the digital ground, if possible. PIN DESCRIPTIONS PIN NO. PIN NAME QFN-56 TQFP-64 I/O DESCRIPTION D13 1 1 I/O Data bit 13 D14 2 2 I/O Data bit 14 D15 3 3 I/O Data bit 15 Analog monitor output. This pin is either in Hi-Z status, or connected to one of the DAC outputs, VMON 4 4 O reference buffer outputs, or offset DAC outputs, depending on the content of the Monitor Register. VOUT-3 5 5 O DAC-3 output REF-A 6 6 I Group A(1) reference input VOUT-2 7 7 O DAC-2 output AVDD 8 8 I Positive analog power supply AGND-A 9 9 I Group A(1) analog ground and the ground of REF-A. This pin must be tied to AGND-B and DGND. VOUT-1 10 10 O DAC-1 output AVSS 11 11 I Negative analog power supply. Connect to AGND in single-supply operation. OFFSET DAC-A analog output. Must be connected to AGND-A during single power-supply operation OFFSET-A 12 12 O (AVSS = 0V). This pin is not intended to drive an external load. VOUT-0 13 13 O DAC-0 output Input data format selection. Input data are in straight binary format when connected to DGND or in twos USB/BTC 14 15 I complement format when connected to IOVDD. Command data are always in straight binary format. This pin is an open drain and requires an external pullup resistor. BUSY goes low when the correction BUSY 15 16 O engine is running; see the Busy Pin section for details. Level trigger. When the CLR pin is logic '0', all VOUT-X pins connect to AGND-x through switches and an CLR 16 17 I internal 15k Ω resistor. When the CLR pin is logic '1' and LDAC is logic '0', all VOUT-X pins connect to the amplifier outputs. (1) Group A consists of DAC-0, DAC-1, DAC-2, and DAC-3. Group B consists of DAC-4, DAC-5, DAC-6, and DAC-7. 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8728 |
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