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SN65HVS882PWP Datasheet(PDF) 6 Page - Texas Instruments |
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SN65HVS882PWP Datasheet(HTML) 6 Page - Texas Instruments |
6 / 23 page TIMING REQUIREMENTS SWITCHING CHARACTERISTICS SN65HVS882 SLAS601 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tW1 CLK pulse duration See Figure 5 4 ns tW2 LD pulse duration See Figure 3 6 ns tSU1 SIP to CLK setup time See Figure 6 4 ns tH1 SIP to CLK hold time See Figure 6 2 ns tSU2 Falling edge to rising edge (CE to CLK) setup time See Figure 7 4 ns tREC LD to CLK recovery time See Figure 4 2 ns fCLK Clock pulse frequency See Figure 5 DC 100 MHz over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH1, tPHL1 CLK to SOP CL = 15 pF, see Figure 5 10 ns tPLH2, tPHL2 LD to SOP CL = 15 pF, see Figure 3 14 ns tr, tf Rise and fall times CL = 15 pF, see Figure 5 5 ns 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65HVS882 |
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