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SN65MLVD048 Datasheet(PDF) 6 Page - Texas Instruments |
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SN65MLVD048 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 20 page SN65MLVD048 SLLS903 – DECEMBER 2009 www.ti.com RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 2 6 ns tPHL Propagation delay time, high-to-low-level output 2 6 ns tr Output signal rise time 1 2.3 tf Output signal fall time CL = 15 pF, See Figure 2 1 2.3 ns Type 1 35 270 tsk(p) Pulse skew (|tPHL – tPLH|) ps Type 2 150 460 tsk(pp) Part-to-part skew 800 ps tjit(per) Period jitter, rms (1 standard deviation)(2) All channels switching, 125 MHz 6 ps clock input(3), See Figure 4 tjit(c-c) Cycle-to-cycle jitter, rms(2) 13 ps Type 1 800 ps tjit(det) Deterministic jitter(2) Type 2 945 ps All channels switching, 250 Mbps 215-1 PRBS input(3), See Figure 4 Type 1 9 ps tjit(ran) Random jitter(2) Type 2 8 ps tPZH Enable time, high-impedance-to-high-level output CL = 15 pF, See Figure 3 15 ns tPZL Enable time, high-impedance-to-low-level output CL = 15 pF, See Figure 3 15 ns tPHZ Disable time, high-level-to-high-impedance output CL = 15 pF, See Figure 3 10 ns tPLZ Disable time, low-level-to-high-impedance output CL = 15 pF, See Figure 3 10 ns (1) All typical values are at 25°C and with a 3.3-V supply voltage. (2) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. (3) tr = tf = 0.5ns (10% to 90%) 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 |
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