CDCE72010RGCRG4 datasheet(6/73 Pages) TI

Part #	CDCE72010RGCRG4

Description	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

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Manufacturer	TI [Texas Instruments]

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RECOMMENDED OPERATING CONDITIONS

CDCE72010

SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com

for the CDCE72010 device for under the specified industrial temperature range of –40°C to 85°C

MIN

NOM

MAX

UNIT

Power Supply

VCC

Supply voltage

3

3.3

3.6

V

VCC_PLL,

VCC_IN,

Analog supply voltage

3

3.3

3.6

VCC_VCXO,

VCCA

VCC_CP

2.3

VCC

V

REF at 30.72MHz VCXO at

Divider 1 set to divide by 8 (DCR

P LVPECL

491.52MHz Outputs are

30%) Divider 2 set to divide by 4

2.9

W

LVPECL-HS

(DCR 30%) Divider 3 set to divide

by 2 (DCR 30%) Divider 4 set to

REF at 30.72MHz VCXO at

P LVDS

2.0

W

divide by 2 (DCR 30%) Divider 5

491.52MHz Outputs are LVDS-HS

set to divide by 1 (DCR 30%)

Divider 6 set to divide by 1 (DCR

0%) Divider 7 set to divide by 1

REF at 30.72MHz VCXO at

P LVCMOS

2.2

W

(DCR 0%) Divider 8 set to divide by

122.88MHz Outputs are LVCMOS

1 (DCR 0%) DCR: Divider Current

Reduction Setting

REF at 30.72MHz VCXO at

Dividers are disabled. Outputs are

P OFF

775

mW

491.52MHz

disabled.

P PD

Device is powered down

30

mW

Typical Operating Conditions at VCC=3.3V and 25°C unless otherwise specified.

Differential Input Mode (PRI_REF, SEC_REF, VCXO_IN and AUX_IN)

VINPP

Input amplitude(1)

(V_INP – VINN)

0.1

1.3

V

VICM

Common-mode input voltage

1.0

VCC– 0.3

V

Differential input current high ( No

IIH

VI = VCC, VCC = 3.6 V

20

µA

internal termination)

Differential input current low( No

IIL

VI = 0 V, VCC = 3.6 V

–20

20

µA

internal termination)

Input capacitance on PRI_REF, SEC_REF and VCXO_REF

3

pF

Input capacitance on AUX_IN

7

pF

LVCMOS Input Mode (SPI_CLK, SPI_MOSI, SPI_LE, PD, RESET, REF_SEL, MOD_SEL)

VIL

Low-level input voltage LVCMOS(2)

0

0.3 VCC

V

VIH

High-level input voltage LVCMOS(2)

0.7 VCC

VCC

V

VIK

LVCMOS input clamp voltage

VCC = 3 V, II = –18 mA

–1.2

V

IIH

LVCMOS input current

VI = VCC, VCC = 3.6 V

20

µA

IIL

LVCMOS input

VI = 0 V, VCC = 3.6 V

–10

–40

µA

CI

Input capacitance (LVCMOS

VI = 0 V or VCC

3

pF

signals)

(1)

VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP of

150mV.

(2)

VIL and VIH are required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an AC coupling

to VCC/2 is provided.

6

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