PHN203

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© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 05 — 27 April 2010

9 of 13

NXP Semiconductors

PHN203

Dual N-channel TrenchMOS logic level FET

7.

Package outline

Fig 14. Package outline SOT96-1 (SO8)

UNIT

A

max.

(1)

QZ

y

w

v

θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

mm

inches

1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

1.27

6.2

5.8

1.05

0.7

0.6

0.7

0.3

8

0

o

o

0.25

0.1

0.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

X

θ

A

D

Q

detail X

E

Z

e

c

L

(A )

3

A

4

5

pin 1 index

1

8

y

076E03

MS-012

0.069

0.010

0.004

0.057

0.049

0.01

0.019

0.014

0.0100

0.0075

0.20

0.19

0.16

0.15

0.05

0.244

0.228

0.028

0.024

0.028

0.012

0.01

0.01

0.041

0.004

0.039

0.016

0

2.5

5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

99-12-27

03-02-18