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PHKD6N02LT Datasheet(PDF) 1 Page - NXP Semiconductors |
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PHKD6N02LT Datasheet(HTML) 1 Page - NXP Semiconductors |
1 / 13 page PHKD6N02LT Dual N-channel TrenchMOS logic level FET Rev. 04 — 27 April 2010 Product data sheet 1. Product profile 1.1 General description Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Low conduction losses due to low on-state resistance Suitable for logic level gate drive sources 1.3 Applications Battery chargers DC-to-DC convertors Notebook computers Portable equipment 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C --20 V ID drain current Tsp = 25 °C; Single device conducting; see Figure 1; see Figure 3 --10.9 A Ptot total power dissipation Tsp =25°C; see Figure 2 --4.17 W Static characteristics RDSon drain-source on-state resistance VGS =2.5 V; ID =3A; Tj = 25 °C - 25 35 m Ω Dynamic characteristics QGD gate-drain charge VGS =5V; ID =6A; VDS =16 V; Tj =25°C; see Figure 11 -6 -nC |
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