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C8051F707-GM Datasheet(PDF) 6 Page - Silicon Laboratories |
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C8051F707-GM Datasheet(HTML) 6 Page - Silicon Laboratories |
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6 / 290 page  C8051F70x/71x 6 Rev. 0.2 26.5. Port Match ..................................................................................................... 176 26.6. Special Function Registers for Accessing and Configuring Port I/O ............. 178 27. Cyclic Redundancy Check Unit (CRC0)............................................................. 194 27.1. 16-bit CRC Algorithm..................................................................................... 195 27.2. 32-bit CRC Algorithm..................................................................................... 196 27.3. Preparing for a CRC Calculation ................................................................... 197 27.4. Performing a CRC Calculation ...................................................................... 197 27.5. Accessing the CRC0 Result .......................................................................... 197 27.6. CRC0 Bit Reverse Feature............................................................................ 200 28. SMBus................................................................................................................... 202 28.1. Supporting Documents .................................................................................. 203 28.2. SMBus Configuration..................................................................................... 203 28.3. SMBus Operation .......................................................................................... 203 28.3.1. Transmitter Vs. Receiver....................................................................... 204 28.3.2. Arbitration.............................................................................................. 204 28.3.3. Clock Low Extension............................................................................. 204 28.3.4. SCL Low Timeout.................................................................................. 204 28.3.5. SCL High (SMBus Free) Timeout ......................................................... 205 28.4. Using the SMBus........................................................................................... 205 28.4.1. SMBus Configuration Register.............................................................. 205 28.4.2. SMB0CN Control Register .................................................................... 209 28.4.2.1. Software ACK Generation ............................................................ 209 28.4.2.2. Hardware ACK Generation ........................................................... 209 28.4.3. Hardware Slave Address Recognition .................................................. 211 28.4.4. Data Register ........................................................................................ 214 28.5. SMBus Transfer Modes................................................................................. 215 28.5.1. Write Sequence (Master) ...................................................................... 215 28.5.2. Read Sequence (Master) ...................................................................... 216 28.5.3. Write Sequence (Slave) ........................................................................ 217 28.5.4. Read Sequence (Slave) ........................................................................ 218 28.6. SMBus Status Decoding................................................................................ 218 29. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 224 29.1. Signal Descriptions........................................................................................ 225 29.1.1. Master Out, Slave In (MOSI)................................................................. 225 29.1.2. Master In, Slave Out (MISO)................................................................. 225 29.1.3. Serial Clock (SCK) ................................................................................ 225 29.1.4. Slave Select (NSS) ............................................................................... 225 29.2. SPI0 Master Mode Operation ........................................................................ 226 29.3. SPI0 Slave Mode Operation .......................................................................... 227 29.4. SPI0 Interrupt Sources .................................................................................. 228 29.5. Serial Clock Phase and Polarity .................................................................... 228 29.6. SPI Special Function Registers ..................................................................... 230 30. UART0 ................................................................................................................... 237 30.1. Enhanced Baud Rate Generation.................................................................. 238 30.2. Operational Modes ........................................................................................ 239 |
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