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PCF8566TS Datasheet(PDF) 7 Page - NXP Semiconductors |
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PCF8566TS Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 48 page PCF8566_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 25 February 2009 7 of 48 NXP Semiconductors PCF8566 Universal LCD driver for low multiplex rates 7.1 Power-on reset At power-on the PCF8566 resets to the following starting conditions: • All backplane outputs are set to VDD • All segment outputs are set to VDD • Drive mode 1:4 multiplex with 1 ⁄3 bias is selected • Blinking is switched off • Input and output bank selectors are reset (as defined in Table 8) • The I2C-bus interface is initialized • The data pointer and the subaddress counter are cleared Do not transfer data on the I2C-bus after a power-on for at least 1 ms to allow the reset action to complete. 7.2 LCD bias generator The full-scale LCD voltage (Voper) is obtained from VDD − VLCD. The LCD voltage may be temperature compensated externally through the VLCD supply to pin 12. Fractional LCD biasing voltages are obtained from an internal voltage divider comprising three series resistors connected between VDD and VLCD. The center resistor can be switched out of the circuit to provide a 1 ⁄ 2 bias voltage level for the 1:2 multiplex configuration. 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by mode-set commands from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 5. Fig 4. Typical system configuration HOST MICRO- PROCESSOR/ MICRO- CONTROLLER SDA SCL OSC 1 17 to 40 13 to 16 2 6 78 512 910 11 24 segment drives 4 backplanes LCD PANEL (up to 96 elements) PCF8566 A0 A1 A2 SA0 VDD VDD VLCD VSS VSS mgg385 R ≤ trise 2 Cbus |
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