PCA9575 datasheet(11/38 Pages) NXP

Part #	PCA9575

Description	16-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

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Manufacturer	NXP [NXP Semiconductors]

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11 / 38 page

PCA9575_3

Product data sheet

Rev. 03 — 9 November 2009

11 of 38

NXP Semiconductors

PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.6.2 Register 1 - Input port 1 register

This register is read-only. It reﬂects the incoming logic levels of the pins, regardless of

whether the pin is deﬁned as an input or an output by the Conﬁguration register. Writes to

this register will be acknowledged but will have no effect.

The default ‘X’ is determined by the externally applied logic level.

7.6.3 Register 2 - Polarity inversion port 0 register

This register allows the user to invert the polarity of the Input port register data. If a bit in

this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in

this register is cleared (written with a ‘0’), the Input port data polarity is retained.

Table 5.

Register 1 - Input port 1 register (address 01h) bit description

Bit

Symbol

Access

Value

Description

7

IO1.7

read only

X

determined by externally applied logic level

6

IO1.6

read only

X

5

IO1.5

read only

X

4

IO1.4

read only

X

3

IO1.3

read only

X

2

IO1.2

read only

X

1

IO1.1

read only

X

0

IO1.0

read only

X

Table 6.

Register 2 - Polarity Inversion port 0 register (address 02h) bit description

Legend: * default value.

Bit

Symbol

Access

Value

Description

7

N0.7

R/W

0*

inverts polarity of Input port 0 register data

0 = Input port 0 register data retained (default value)

1 = Input port 0 register data inverted

6

N0.6

R/W

0*

5

N0.5

R/W

0*

4

N0.4

R/W

0*

3

N0.3

R/W

0*

2

N0.2

R/W

0*

1

N0.1

R/W

0*

0

N0.0

R/W

0*

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