PCA9545A_45B_45C_7

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 07 — 19 June 2009

8 of 28

NXP Semiconductors

PCA9545A/45B/45C

6.2.2 Interrupt handling

The PCA9545A/45B/45C provides 4 interrupt inputs, one for each channel, and one

open-drain interrupt output. When an interrupt is generated by any device, it will be

detected by the PCA9545A/45B/45C and the interrupt output will be driven LOW. The

channel does not need to be active for detection of the interrupt. A bit is also set in the

control register.

Bit 4 through bit 7 of the control register corresponds to channel 0 through channel 3 of

the PCA9545A/45B/45C, respectively. Therefore, if an interrupt is generated by any

device connected to channel 1, the state of the interrupt inputs is loaded into the control

register when a read is accomplished. Likewise, an interrupt on any device connected to

channel 0 would cause bit 4 of the control register to be set on the read. The master can

then address the PCA9545A/45B/45C and read the contents of the control register to

determine which channel contains the device generating the interrupt. The master can

then reconfigure the PCA9545A/45B/45C to select this channel, and locate the device

generating the interrupt and clear it.

It should be noted that more than one device can provide an interrupt on a channel, so it is

up to the master to ensure that all devices on a channel are interrogated for an interrupt.

The interrupt inputs may be used as general purpose inputs if the interrupt function is not

required.

Remark: Several interrupts can be active at the same time. Example: INT3 = 0, INT2 = 1,

INT1 = 1, INT0 = 0, means that there is no interrupt on channel 0 and channel 3, and

there is interrupt on channel 1 and channel 2.

6.3 RESET input

The RESET input is an active LOW signal which may be used to recover from a bus fault

Table 5.

Control register: Read—interrupt

INT3

INT2

INT1

INT0

B3

B2

B1

B0

Command

XXX

0

XXXX

no interrupt on channel 0

1

interrupt on channel 0

XX

0

XXXXX

no interrupt on channel 1

1

interrupt on channel 1

X

0

XXXXXX

no interrupt on channel 2

1

interrupt on channel 2

0

XXXXXXX

no interrupt on channel 3

1

interrupt on channel 3