PCA9515A_4

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 — 11 April 2008

5 of 18

NXP Semiconductors

PCA9515A

7.

Application design-in information

A typical application is shown in Figure 4. In this example, the system master is running

unless the slave bus is isolated and then the master bus can run at 400 kHz. Master

devices can be placed on either bus.

The PCA9515A is 5 V tolerant, so it does not require any additional circuitry to translate

between the different bus voltages.

hysteresis type input detects the falling edge and causes the internal driver on the other

side to turn on, thus causing the other side to also go LOW. The side driven LOW by the

In order to illustrate what would be seen in a typical application, refer to Figure 5 and

Figure 6. If the bus master in Figure 4 were to write to the slave through the PCA9515A,

of the PCA9515A is typically round 0.5 V, a step in the SDA will be seen. After the master

On the bus 1 side of the PCA9515A, the clock and data lines would have a positive offset

important to note that any arbitration or clock stretching events on bus 1 require that the

by the PCA9515A and then transmitted to bus 0.

Fig 4.

Typical application

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PCA9515A

SDA0

SDA1

SCL0

SCL1

EN

10 k

Ω

10 k

Ω

SDA

SCL

BUS

MASTER

400 kHz

SLAVE

100 kHz

SDA

SCL

bus 0

bus 1

5 V

3.3 V

10 k

Ω

10 k

Ω