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S9S08SG8E2VRSCR Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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S9S08SG8E2VRSCR Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
10 / 316 page MC9S08SG8 MCU Series Data Sheet, Rev. 6 10 Freescale Semiconductor Section Number Title Page 4.5.3 Program and Erase Command Execution .........................................................................47 4.5.4 Burst Program Execution ..................................................................................................48 4.5.5 Access Errors ....................................................................................................................50 4.5.6 FLASH Block Protection ..................................................................................................50 4.5.7 Vector Redirection ............................................................................................................51 4.6 Security ............................................................................................................................................51 4.7 FLASH Registers and Control Bits .................................................................................................52 4.7.1 FLASH Clock Divider Register (FCDIV) ........................................................................53 4.7.2 FLASH Options Register (FOPT and NVOPT) ................................................................54 4.7.3 FLASH Configuration Register (FCNFG) ........................................................................55 4.7.4 FLASH Protection Register (FPROT and NVPROT) .......................................................55 4.7.5 FLASH Status Register (FSTAT) ......................................................................................56 4.7.6 FLASH Command Register (FCMD) ...............................................................................57 Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction .....................................................................................................................................58 5.2 Features ...........................................................................................................................................58 5.3 MCU Reset ......................................................................................................................................58 5.4 Computer Operating Properly (COP) Watchdog .............................................................................59 5.5 Interrupts .........................................................................................................................................60 5.5.1 Interrupt Stack Frame .......................................................................................................61 5.5.2 Interrupt Vectors, Sources, and Local Masks ....................................................................62 5.6 Low-Voltage Detect (LVD) System ................................................................................................64 5.6.1 Power-On Reset Operation ...............................................................................................64 5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................64 5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................64 5.7 Reset, Interrupt, and System Control Registers and Control Bits ...................................................64 5.7.1 System Reset Status Register (SRS) .................................................................................65 5.7.2 System Background Debug Force Reset Register (SBDFR) ............................................66 5.7.3 System Options Register 1 (SOPT1) ................................................................................67 5.7.4 System Options Register 2 (SOPT2) ................................................................................68 5.7.5 System Device Identification Register (SDIDH, SDIDL) ................................................69 5.7.6 System Power Management Status and Control 1 Register (SPMSC1) ...........................70 5.7.7 System Power Management Status and Control 2 Register (SPMSC2) ...........................71 Chapter 6 Parallel Input/Output Control 6.1 Port Data and Data Direction ..........................................................................................................72 6.2 Pull-up, Slew Rate, and Drive Strength ...........................................................................................73 6.3 Ganged Output ................................................................................................................................74 6.4 Pin Interrupts ...................................................................................................................................75 |
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